#ifndef _ARCH_ARM_AT91_PS_H_
#define _ARCH_ARM_AT91_PS_H_

/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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/*!
 * \file arch/arm/at91_ps.h
 * \brief AT91 peripherals.
 *
 * \verbatim
 *
 * $Log: at91_ps.h,v $
 * Revision 1.1  2006/07/05 07:45:28  haraldkipp
 * Split on-chip interface definitions.
 *
 *
 * \endverbatim
 */

/*!
 * \addtogroup xgNutArchArmAt91Ps
 */
/*@{*/

/*!
 * \name PS Control Register
 */
/*@{*/

/*! \brief Register address.
 *
 * This register allows to stop the CPU clock. The clock is automatically
 * enabled after reset and by any interrupt.
 */
#define PS_CR       (PS_BASE + 0x00)
/*@}*/

/*!
 * \name Peripheral Clock Control Registers
 */
/*@{*/
#define PS_PCER     (PS_BASE + 0x04)    /*!< \brief Peripheral clock enable register address. */
#define PS_PCDR     (PS_BASE + 0x08)    /*!< \brief Peripheral clock disable register address. */
#define PS_PCSR     (PS_BASE + 0x0C)    /*!< \brief Peripheral clock status register address. */
/*@}*/

/*@} xgNutArchArmAt91Ps */

#endif                          /* _ARCH_ARM_AT91_PS_H_ */