#
# Init CPU and init SDRAM was taken from the EIR init script
# More information about the EIR can be found here:
# http://www.ethernut.de/en/hardware/eir/index.html
#


# 
# Init CPU
#

# Disable watchdog
mww 0xfffffd44 0x00008000 # WDT_MR_OFF 

# Use 2 cycles for flash access
mww 0xffffff60 0x00000100 # MC_FMR_OFF

# Disable all interrupts
mww 0xfffff130 0xffffffff # AIC_EOICR_OFF	
mww 0xfffff124 0xffffffff # AIC_IDCR_OFF	

#
# Enable the main oscillator. Set startup time of 6 * 8 slow 
# clock cycles and wait until oscillator is stabilized.
#
mww 0xFFFFFC20 0x00000601 # CKGR_MOR_OFF
sleep 10

#
# Set PLL:
# PLLfreq = crystal / divider * (multiplier + 1)
# Wait 28 clock cycles until PLL is locked.
#
mww 0xFFFFFC2C 0x00481c0e # CKGR_PLLR_OFF
sleep 10

#
# Set master clock prescaler.
#
mww 0xFFFFFC30 0x00000004 # PMC_MCKR_OFF
sleep 10

#
# Switch to PLL clock.
#
mww 0xFFFFFC30 0x00000007 # PMC_MCKR_OFF
sleep 10


#
# Enable SDRAM interface
#

# Enable SDRAM control at PIO A.
mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
mww 0xfffff404 0x3f800000 # PIO_PDR_OFF

# Enable address bus (A0, A2-A11, A13-A17) at PIO B
mww 0xfffff674 0x0003effd # PIO_BSR_OFF
mww 0xfffff604 0x0003effd # PIO_PDR_OFF

# Enable 16 bit data bus at PIO C
mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
mww 0xfffff804 0x0000ffff # PIO_PDR_OFF

# Enable SDRAM chip select
mww 0xffffff80 0x00000002 # EBI_CSA_OFF

# Set SDRAM characteristics in configuration register.
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
sleep 10

# Issue 16 bit SDRAM command: NOP
mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 

# Issue 16 bit SDRAM command: Precharge all
mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 

# Issue 8 auto-refresh cycles
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000 

# Issue 16 bit SDRAM command: Set mode register  
mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
mww 0x20000014 0xcafedede

# Set refresh rate count ???
mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF

# Issue 16 bit SDRAM command: Normal mode
mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
mww 0x20000000 0x00000180

#
# Enable external reset key.
#
mww 0xfffffd08 0xa5000001