2.3-InternetRadio/include/arch/arm/at91_dbgu.h

#ifndef _ARCH_ARM_AT91_DBGU_H_
#define _ARCH_ARM_AT91_DBGU_H_

/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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/*!
 * \file arch/arm/at91_dbgu.h
 * \brief AT91 peripherals.
 *
 * \verbatim
 *
 * $Log: at91_dbgu.h,v $
 * Revision 1.2  2006/08/05 11:54:45  haraldkipp
 * PDC registers added.
 *
 * Revision 1.1  2006/07/05 07:45:25  haraldkipp
 * Split on-chip interface definitions.
 *
 *
 * \endverbatim
 */

/*!
 * \addtogroup xgNutArchArmAt91Dbgu
 */
/*@{*/

#define DBGU_CR     (DBGU_BASE + US_CR_OFF)     /*!< \brief DBGU control register address. */
#define DBGU_MR     (DBGU_BASE + US_MR_OFF)     /*!< \brief DBGU mode register address. */
#define DBGU_IER    (DBGU_BASE + US_IER_OFF)    /*!< \brief DBGU interrupt enable register address. */
#define DBGU_IDR    (DBGU_BASE + US_IDR_OFF)    /*!< \brief DBGU interrupt disable register address. */
#define DBGU_IMR    (DBGU_BASE + US_IMR_OFF)    /*!< \brief DBGU interrupt mask register address. */
#define DBGU_SR     (DBGU_BASE + US_CSR_OFF)    /*!< \brief DBGU status register address. */
#define DBGU_RHR    (DBGU_BASE + US_RHR_OFF)    /*!< \brief DBGU receiver holding register address. */
#define DBGU_THR    (DBGU_BASE + US_THR_OFF)    /*!< \brief DBGU transmitter holding register address. */
#define DBGU_BRGR   (DBGU_BASE + US_BRGR_OFF)   /*!< \brief DBGU baud rate register address. */

#define DBGU_CIDR_OFF           0x00000040      /*!< \brief DBGU chip ID register offset. */
#define DBGU_CIDR   (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */

#define DBGU_EXID_OFF           0x00000044      /*!< \brief DBGU chip ID extension register offset. */
#define DBGU_EXID   (DBGU_BASE + DBGU_EXID_OFF) /*!< \brief DBGU chip ID extension register. */

#define DBGU_FNR_OFF            0x00000048      /*!< \brief DBGU force NTRST register offset. */
#define DBGU_FNR    (DBGU_BASE + DBGU_FNR_OFF)  /*!< \brief DBGU force NTRST register. */

#if defined(DBGU_HAS_PDC)
#define DBGU_RPR    (DBGU_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC receive pointer register. */
#define DBGU_RCR    (DBGU_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC receive counter register. */
#define DBGU_TPR    (DBGU_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC transmit pointer register. */
#define DBGU_TCR    (DBGU_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC transmit counter register. */
#define DBGU_RNPR   (DBGU_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC receive next pointer register. */
#define DBGU_RNCR   (DBGU_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC receive next counter register. */
#define DBGU_TNPR   (DBGU_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC transmit next pointer register. */
#define DBGU_TNCR   (DBGU_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC transmit next counter register. */
#define DBGU_PTCR   (DBGU_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC transfer control register. */
#define DBGU_PTSR   (DBGU_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC transfer status register. */
#endif

/*@} xgNutArchArmAt91Dbgu */

#endif                          /* _ARCH_ARM_AT91_DBGU_H_ */