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2.3-InternetRad...
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include
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arch
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arm
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at91_pio.h

at91_pio.h 18 KB
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  1. #ifndef _ARCH_ARM_AT91_PIO_H_
    2. 

  2. #define _ARCH_ARM_AT91_PIO_H_
    3. 

  3. 

  4. /*
    5. 

  5.  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
    6. 

  6.  *
    7. 

  7.  * Redistribution and use in source and binary forms, with or without
    8. 

  8.  * modification, are permitted provided that the following conditions
    9. 

  9.  * are met:
    10. 

  10.  *
    11. 

  11.  * 1. Redistributions of source code must retain the above copyright
    12. 

  12.  *    notice, this list of conditions and the following disclaimer.
    13. 

  13.  * 2. Redistributions in binary form must reproduce the above copyright
    14. 

  14.  *    notice, this list of conditions and the following disclaimer in the
    15. 

  15.  *    documentation and/or other materials provided with the distribution.
    16. 

  16.  * 3. Neither the name of the copyright holders nor the names of
    17. 

  17.  *    contributors may be used to endorse or promote products derived
    18. 

  18.  *    from this software without specific prior written permission.
    19. 

  19.  *
    20. 

  20.  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
    21. 

  21.  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    22. 

  22.  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
    23. 

  23.  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
    24. 

  24.  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    25. 

  25.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    26. 

  26.  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    27. 

  27.  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
    28. 

  28.  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
    29. 

  29.  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
    30. 

  30.  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
    31. 

  31.  * SUCH DAMAGE.
    32. 

  32.  *
    33. 

  33.  * For additional information see http://www.ethernut.de/
    34. 

  34.  */
    35. 

  35. 

  36. /*!
    37. 

  37.  * \file arch/arm/at91_pio.h
    38. 

  38.  * \brief AT91 peripherals.
    39. 

  39.  *
    40. 

  40.  * \verbatim
    41. 

  41.  *
    42. 

  42.  * $Log: at91_pio.h,v $
    43. 

  43.  * Revision 1.3  2006/09/29 12:43:08  haraldkipp
    44. 

  44.  * Register offsets added, which are quite useful for assembler programming.
    45. 

  45.  * Added some special PIO features, which are available on the AT91SAM92xx
    46. 

  46.  * series.
    47. 

  47.  *
    48. 

  48.  * Revision 1.2  2006/08/31 19:11:18  haraldkipp
    49. 

  49.  * Added register definitions for PIOC.
    50. 

  50.  *
    51. 

  51.  * Revision 1.1  2006/07/05 07:45:28  haraldkipp
    52. 

  52.  * Split on-chip interface definitions.
    53. 

  53.  *
    54. 

  54.  *
    55. 

  55.  * \endverbatim
    56. 

  56.  */
    57. 

  57. 

  58. /*!
    59. 

  59.  * \addtogroup xgNutArchArmAt91Pio
    60. 

  60.  */
    61. 

  61. /*@{*/
    62. 

  62. 

  63. /*! \name PIO Register Offsets */
    64. 

  64. /*@{*/
    65. 

  65. #define PIO_PER_OFF     0x00000000  /*!< \brief PIO enable register offset. */
    66. 

  66. #define PIO_PDR_OFF     0x00000004  /*!< \brief PIO disable register offset. */
    67. 

  67. #define PIO_PSR_OFF     0x00000008  /*!< \brief PIO status register offset. */
    68. 

  68. #define PIO_OER_OFF     0x00000010  /*!< \brief Output enable register offset. */
    69. 

  69. #define PIO_ODR_OFF     0x00000014  /*!< \brief Output disable register offset. */
    70. 

  70. #define PIO_OSR_OFF     0x00000018  /*!< \brief Output status register offset. */
    71. 

  71. #define PIO_IFER_OFF    0x00000020  /*!< \brief Input filter enable register offset. */
    72. 

  72. #define PIO_IFDR_OFF    0x00000024  /*!< \brief Input filter disable register offset. */
    73. 

  73. #define PIO_IFSR_OFF    0x00000028  /*!< \brief Input filter status register offset. */
    74. 

  74. #define PIO_SODR_OFF    0x00000030  /*!< \brief Set output data register offset. */
    75. 

  75. #define PIO_CODR_OFF    0x00000034  /*!< \brief Clear output data register offset. */
    76. 

  76. #define PIO_ODSR_OFF    0x00000038  /*!< \brief Output data status register offset. */
    77. 

  77. #define PIO_PDSR_OFF    0x0000003C  /*!< \brief Pin data status register offset. */
    78. 

  78. #define PIO_IER_OFF     0x00000040  /*!< \brief Interrupt enable register offset. */
    79. 

  79. #define PIO_IDR_OFF     0x00000044  /*!< \brief Interrupt disable register offset. */
    80. 

  80. #define PIO_IMR_OFF     0x00000048  /*!< \brief Interrupt mask register offset. */
    81. 

  81. #define PIO_ISR_OFF     0x0000004C  /*!< \brief Interrupt status register offset. */
    82. 

  82. #if defined(PIO_HAS_MULTIDRIVER)
    83. 

  83. #define PIO_MDER_OFF    0x00000050  /*!< \brief Multi-driver enable register offset. */
    84. 

  84. #define PIO_MDDR_OFF    0x00000054  /*!< \brief Multi-driver disable register offset. */
    85. 

  85. #define PIO_MDSR_OFF    0x00000058  /*!< \brief Multi-driver status register offset. */
    86. 

  86. #endif /* PIO_HAS_MULTIDRIVER */
    87. 

  87. #if defined(PIO_HAS_PULLUP)
    88. 

  88. #define PIO_PUDR_OFF    0x00000060  /*!< \brief Pull-up disable register offset. */
    89. 

  89. #define PIO_PUER_OFF    0x00000064  /*!< \brief Pull-up enable register offset. */
    90. 

  90. #define PIO_PUSR_OFF    0x00000068  /*!< \brief Pull-up status register offset. */
    91. 

  91. #endif /* PIO_HAS_PULLUP */
    92. 

  92. #if defined(PIO_HAS_PERIPHERALSELECT)
    93. 

  93. #define PIO_ASR_OFF     0x00000070  /*!< \brief PIO peripheral A select register offset. */
    94. 

  94. #define PIO_BSR_OFF     0x00000074  /*!< \brief PIO peripheral B select register offset. */
    95. 

  95. #define PIO_ABSR_OFF    0x00000078  /*!< \brief PIO peripheral AB status register offset. */
    96. 

  96. #endif /* PIO_HAS_PERIPHERALSELECT */
    97. 

  97. #if defined(PIO_HAS_OUTPUTWRITEENABLE)
    98. 

  98. #define PIO_OWER_OFF    0x000000A0  /*!< \brief PIO output write enable register offset. */
    99. 

  99. #define PIO_OWDR_OFF    0x000000A4  /*!< \brief PIO output write disable register offset. */
    100. 

  100. #define PIO_OWSR_OFF    0x000000A8  /*!< \brief PIO output write status register offset. */
    101. 

  101. #endif /* PIO_HAS_OUTPUTWRITEENABLE */
    102. 

  102. /*@}*/
    103. 

  103. 

  104. /*! \name Single PIO Register Addresses */
    105. 

  105. /*@{*/
    106. 

  106. #if defined(PIO_BASE)
    107. 

  107. #define PIO_PER     (PIO_BASE + PIO_PER_OFF)    /*!< \brief PIO enable register address. */
    108. 

  108. #define PIO_PDR     (PIO_BASE + PIO_PDR_OFF)    /*!< \brief PIO disable register address. */
    109. 

  109. #define PIO_PSR     (PIO_BASE + PIO_PSR_OFF)    /*!< \brief PIO status register address. */
    110. 

  110. #define PIO_OER     (PIO_BASE + PIO_OER_OFF)    /*!< \brief Output enable register address. */
    111. 

  111. #define PIO_ODR     (PIO_BASE + PIO_ODR_OFF)    /*!< \brief Output disable register address. */
    112. 

  112. #define PIO_OSR     (PIO_BASE + PIO_OSR_OFF)    /*!< \brief Output status register address. */
    113. 

  113. #define PIO_IFER    (PIO_BASE + PIO_IFER_OFF)   /*!< \brief Input filter enable register address. */
    114. 

  114. #define PIO_IFDR    (PIO_BASE + PIO_IFDR_OFF)   /*!< \brief Input filter disable register address. */
    115. 

  115. #define PIO_IFSR    (PIO_BASE + PIO_IFSR_OFF)   /*!< \brief Input filter status register address. */
    116. 

  116. #define PIO_SODR    (PIO_BASE + PIO_SODR_OFF)   /*!< \brief Set output data register address. */
    117. 

  117. #define PIO_CODR    (PIO_BASE + PIO_CODR_OFF)   /*!< \brief Clear output data register address. */
    118. 

  118. #define PIO_ODSR    (PIO_BASE + PIO_ODSR_OFF)   /*!< \brief Output data status register address. */
    119. 

  119. #define PIO_PDSR    (PIO_BASE + PIO_PDSR_OFF)   /*!< \brief Pin data status register address. */
    120. 

  120. #define PIO_IER     (PIO_BASE + PIO_IER_OFF)    /*!< \brief Interrupt enable register address. */
    121. 

  121. #define PIO_IDR     (PIO_BASE + PIO_IDR_OFF)    /*!< \brief Interrupt disable register address. */
    122. 

  122. #define PIO_IMR     (PIO_BASE + PIO_IMR_OFF)    /*!< \brief Interrupt mask register address. */
    123. 

  123. #define PIO_ISR     (PIO_BASE + PIO_ISR_OFF)    /*!< \brief Interrupt status register address. */
    124. 

  124. #if defined(PIO_HAS_MULTIDRIVER)
    125. 

  125. #define PIO_MDER    (PIO_BASE + PIO_MDER_OFF)   /*!< \brief Multi-driver enable register address. */
    126. 

  126. #define PIO_MDDR    (PIO_BASE + PIO_MDDR_OFF)   /*!< \brief Multi-driver disable register address. */
    127. 

  127. #define PIO_MDSR    (PIO_BASE + PIO_MDSR_OFF)   /*!< \brief Multi-driver status register address. */
    128. 

  128. #endif /* PIO_HAS_MULTIDRIVER */
    129. 

  129. #if defined(PIO_HAS_PULLUP)
    130. 

  130. #define PIO_PUDR    (PIO_BASE + PIO_PUDR_OFF)   /*!< \brief Pull-up disable register address. */
    131. 

  131. #define PIO_PUER    (PIO_BASE + PIO_PUER_OFF)   /*!< \brief Pull-up enable register address. */
    132. 

  132. #define PIO_PUSR    (PIO_BASE + PIO_PUSR_OFF)   /*!< \brief Pull-up status register address. */
    133. 

  133. #endif /* PIO_HAS_PULLUP */
    134. 

  134. #if defined(PIO_HAS_PERIPHERALSELECT)
    135. 

  135. #define PIO_ASR     (PIO_BASE + PIO_ASR_OFF)    /*!< \brief PIO peripheral A select register address. */
    136. 

  136. #define PIO_BSR     (PIO_BASE + PIO_BSR_OFF)    /*!< \brief PIO peripheral B select register address. */
    137. 

  137. #define PIO_ABSR    (PIO_BASE + PIO_ABSR_OFF)   /*!< \brief PIO peripheral AB status register address. */
    138. 

  138. #endif /* PIO_HAS_PERIPHERALSELECT */
    139. 

  139. #if defined(PIO_HAS_OUTPUTWRITEENABLE)
    140. 

  140. #define PIO_OWER    (PIO_BASE + PIO_OWER_OFF)   /*!< \brief PIO output write enable register address. */
    141. 

  141. #define PIO_OWDR    (PIO_BASE + PIO_OWDR_OFF)   /*!< \brief PIO output write disable register address. */
    142. 

  142. #define PIO_OWSR    (PIO_BASE + PIO_OWSR_OFF)   /*!< \brief PIO output write status register address. */
    143. 

  143. #endif /* PIO_HAS_OUTPUTWRITEENABLE */
    144. 

  144. #endif /* PIO_BASE */
    145. 

  145. /*@}*/
    146. 

  146. 

  147. /*! \name PIO A Register Addresses */
    148. 

  148. /*@{*/
    149. 

  149. #if defined(PIOA_BASE)
    150. 

  150. #define PIOA_PER    (PIOA_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
    151. 

  151. #define PIOA_PDR    (PIOA_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
    152. 

  152. #define PIOA_PSR    (PIOA_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
    153. 

  153. #define PIOA_OER    (PIOA_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
    154. 

  154. #define PIOA_ODR    (PIOA_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
    155. 

  155. #define PIOA_OSR    (PIOA_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
    156. 

  156. #define PIOA_IFER   (PIOA_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
    157. 

  157. #define PIOA_IFDR   (PIOA_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
    158. 

  158. #define PIOA_IFSR   (PIOA_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
    159. 

  159. #define PIOA_SODR   (PIOA_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
    160. 

  160. #define PIOA_CODR   (PIOA_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
    161. 

  161. #define PIOA_ODSR   (PIOA_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
    162. 

  162. #define PIOA_PDSR   (PIOA_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
    163. 

  163. #define PIOA_IER    (PIOA_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
    164. 

  164. #define PIOA_IDR    (PIOA_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
    165. 

  165. #define PIOA_IMR    (PIOA_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
    166. 

  166. #define PIOA_ISR    (PIOA_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
    167. 

  167. #if defined(PIO_HAS_MULTIDRIVER)
    168. 

  168. #define PIOA_MDER   (PIOA_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
    169. 

  169. #define PIOA_MDDR   (PIOA_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
    170. 

  170. #define PIOA_MDSR   (PIOA_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
    171. 

  171. #endif /* PIO_HAS_MULTIDRIVER */
    172. 

  172. #if defined(PIO_HAS_PULLUP)
    173. 

  173. #define PIOA_PUDR   (PIOA_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
    174. 

  174. #define PIOA_PUER   (PIOA_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
    175. 

  175. #define PIOA_PUSR   (PIOA_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
    176. 

  176. #endif /* PIO_HAS_PULLUP */
    177. 

  177. #if defined(PIO_HAS_PERIPHERALSELECT)
    178. 

  178. #define PIOA_ASR    (PIOA_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
    179. 

  179. #define PIOA_BSR    (PIOA_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
    180. 

  180. #define PIOA_ABSR   (PIOA_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
    181. 

  181. #endif /* PIO_HAS_PERIPHERALSELECT */
    182. 

  182. #if defined(PIO_HAS_OUTPUTWRITEENABLE)
    183. 

  183. #define PIOA_OWER   (PIOA_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
    184. 

  184. #define PIOA_OWDR   (PIOA_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
    185. 

  185. #define PIOA_OWSR   (PIOA_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
    186. 

  186. #endif /* PIO_HAS_OUTPUTWRITEENABLE */
    187. 

  187. #endif /* PIOA_BASE */
    188. 

  188. /*@}*/
    189. 

  189. 

  190. /*! \name PIO B Register Addresses */
    191. 

  191. /*@{*/
    192. 

  192. #if defined(PIOB_BASE)
    193. 

  193. #define PIOB_PER    (PIOB_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
    194. 

  194. #define PIOB_PDR    (PIOB_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
    195. 

  195. #define PIOB_PSR    (PIOB_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
    196. 

  196. #define PIOB_OER    (PIOB_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
    197. 

  197. #define PIOB_ODR    (PIOB_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
    198. 

  198. #define PIOB_OSR    (PIOB_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
    199. 

  199. #define PIOB_IFER   (PIOB_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
    200. 

  200. #define PIOB_IFDR   (PIOB_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
    201. 

  201. #define PIOB_IFSR   (PIOB_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
    202. 

  202. #define PIOB_SODR   (PIOB_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
    203. 

  203. #define PIOB_CODR   (PIOB_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
    204. 

  204. #define PIOB_ODSR   (PIOB_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
    205. 

  205. #define PIOB_PDSR   (PIOB_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
    206. 

  206. #define PIOB_IER    (PIOB_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
    207. 

  207. #define PIOB_IDR    (PIOB_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
    208. 

  208. #define PIOB_IMR    (PIOB_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
    209. 

  209. #define PIOB_ISR    (PIOB_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
    210. 

  210. #if defined(PIO_HAS_MULTIDRIVER)
    211. 

  211. #define PIOB_MDER   (PIOB_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
    212. 

  212. #define PIOB_MDDR   (PIOB_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
    213. 

  213. #define PIOB_MDSR   (PIOB_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
    214. 

  214. #endif /* PIO_HAS_MULTIDRIVER */
    215. 

  215. #if defined(PIO_HAS_PULLUP)
    216. 

  216. #define PIOB_PUDR   (PIOB_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
    217. 

  217. #define PIOB_PUER   (PIOB_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
    218. 

  218. #define PIOB_PUSR   (PIOB_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
    219. 

  219. #endif /* PIO_HAS_PULLUP */
    220. 

  220. #if defined(PIO_HAS_PERIPHERALSELECT)
    221. 

  221. #define PIOB_ASR    (PIOB_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
    222. 

  222. #define PIOB_BSR    (PIOB_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
    223. 

  223. #define PIOB_ABSR   (PIOB_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
    224. 

  224. #endif /* PIO_HAS_PERIPHERALSELECT */
    225. 

  225. #if defined(PIO_HAS_OUTPUTWRITEENABLE)
    226. 

  226. #define PIOB_OWER   (PIOB_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
    227. 

  227. #define PIOB_OWDR   (PIOB_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
    228. 

  228. #define PIOB_OWSR   (PIOB_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
    229. 

  229. #endif /* PIO_HAS_OUTPUTWRITEENABLE */
    230. 

  230. #endif /* PIOB_BASE */
    231. 

  231. /*@}*/
    232. 

  232. 

  233. /*! \name PIO C Register Addresses */
    234. 

  234. /*@{*/
    235. 

  235. #if defined(PIOC_BASE)
    236. 

  236. #define PIOC_PER    (PIOC_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
    237. 

  237. #define PIOC_PDR    (PIOC_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
    238. 

  238. #define PIOC_PSR    (PIOC_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
    239. 

  239. #define PIOC_OER    (PIOC_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
    240. 

  240. #define PIOC_ODR    (PIOC_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
    241. 

  241. #define PIOC_OSR    (PIOC_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
    242. 

  242. #define PIOC_IFER   (PIOC_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
    243. 

  243. #define PIOC_IFDR   (PIOC_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
    244. 

  244. #define PIOC_IFSR   (PIOC_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
    245. 

  245. #define PIOC_SODR   (PIOC_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
    246. 

  246. #define PIOC_CODR   (PIOC_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
    247. 

  247. #define PIOC_ODSR   (PIOC_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
    248. 

  248. #define PIOC_PDSR   (PIOC_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
    249. 

  249. #define PIOC_IER    (PIOC_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
    250. 

  250. #define PIOC_IDR    (PIOC_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
    251. 

  251. #define PIOC_IMR    (PIOC_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
    252. 

  252. #define PIOC_ISR    (PIOC_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
    253. 

  253. #if defined(PIO_HAS_MULTIDRIVER)
    254. 

  254. #define PIOC_MDER   (PIOC_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
    255. 

  255. #define PIOC_MDDR   (PIOC_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
    256. 

  256. #define PIOC_MDSR   (PIOC_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
    257. 

  257. #endif /* PIO_HAS_MULTIDRIVER */
    258. 

  258. #if defined(PIO_HAS_PULLUP)
    259. 

  259. #define PIOC_PUDR   (PIOC_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
    260. 

  260. #define PIOC_PUER   (PIOC_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
    261. 

  261. #define PIOC_PUSR   (PIOC_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
    262. 

  262. #endif /* PIO_HAS_PULLUP */
    263. 

  263. #if defined(PIO_HAS_PERIPHERALSELECT)
    264. 

  264. #define PIOC_ASR    (PIOC_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
    265. 

  265. #define PIOC_BSR    (PIOC_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
    266. 

  266. #define PIOC_ABSR   (PIOC_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
    267. 

  267. #endif /* PIO_HAS_PERIPHERALSELECT */
    268. 

  268. #if defined(PIO_HAS_OUTPUTWRITEENABLE)
    269. 

  269. #define PIOC_OWER   (PIOC_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
    270. 

  270. #define PIOC_OWDR   (PIOC_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
    271. 

  271. #define PIOC_OWSR   (PIOC_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
    272. 

  272. #endif /* PIO_HAS_OUTPUTWRITEENABLE */
    273. 

  273. #endif /* PIOC_BASE */
    274. 

  274. /*@}*/
    275. 

  275. 

  276. /*@} xgNutArchArmAt91Pio */
    277. 

  277. 

  278. #endif                          /* _ARCH_ARM_AT91_PIO_H_ */
    279.