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2.3-InternetRad...
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include
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arch
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arm
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at91_spi.h

at91_spi.h 13 KB
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  1. #ifndef _ARCH_ARM_AT91_SPI_H_
    2. 

  2. #define _ARCH_ARM_AT91_SPI_H_
    3. 

  3. 

  4. /*
    5. 

  5.  * Copyright (C)
    6. 

  6.  */
    7. 

  7. 

  8. /*!
    9. 

  9.  * \file arch/arm/at91_spi.h
    10. 

  10.  * \brief AT91 peripherals.
    11. 

  11.  *
    12. 

  12.  * \verbatim
    13. 

  13.  *
    14. 

  14.  * $Log: at91_spi.h,v $
    15. 

  15.  * Revision 1.5  2006/09/29 12:30:31  haraldkipp
    16. 

  16.  * Register offsets added.
    17. 

  17.  *
    18. 

  18.  * Revision 1.4  2006/08/31 19:11:46  haraldkipp
    19. 

  19.  * Bits per transfer definitions added.
    20. 

  20.  *
    21. 

  21.  * Revision 1.3  2006/08/05 11:54:45  haraldkipp
    22. 

  22.  * PDC registers added.
    23. 

  23.  *
    24. 

  24.  * Revision 1.2  2006/07/26 11:22:31  haraldkipp
    25. 

  25.  * Added missing bit definitions.
    26. 

  26.  *
    27. 

  27.  * Revision 1.1  2006/07/21 09:03:56  haraldkipp
    28. 

  28.  * Added SPI support, kindly contributed by Andras Albert.
    29. 

  29.  *
    30. 

  30.  * Revision 1.1
    31. 

  31.  *
    32. 

  32.  *
    33. 

  33.  * \endverbatim
    34. 

  34.  */
    35. 

  35. 

  36. /*!
    37. 

  37.  * \addtogroup xgNutArchArmAt91Spi
    38. 

  38.  */
    39. 

  39. /*@{*/
    40. 

  40. 

  41. /*! \name SPI Control Register */
    42. 

  42. /*@{*/
    43. 

  43. #define	SPI_CR_OFF	    0x00000000  /*!< \brief Control register offset. */
    44. 

  44. 

  45. #define SPI_SPIEN       0x00000001  /*!< \brief SPI enable. */
    46. 

  46. #define SPI_SPIDIS      0x00000002  /*!< \brief SPI disable. */
    47. 

  47. #define SPI_SWRST       0x00000080  /*!< \brief Software reset. */
    48. 

  48. #define SPI_LASTXFER    0x01000000  /*!< \brief Last transfer. */
    49. 

  49. /*@}*/
    50. 

  50. 

  51. /*! \name SPI Mode Register */
    52. 

  52. /*@{*/
    53. 

  53. #define SPI_MR_OFF		0x00000004  /*!< \brief Mode register offset. */
    54. 

  54. 

  55. #define SPI_MSTR        0x00000001  /*!< \brief Master mode. */
    56. 

  56. #define SPI_PS          0x00000002  /*!< \brief Peripheral select. */
    57. 

  57. #define SPI_PCSDEC      0x00000004  /*!< \brief Chip select decode. */
    58. 

  58. #define SPI_FDIV        0x00000008  /*!< \brief Clock selection. */
    59. 

  59. #define SPI_MODFDIS     0x00000010  /*!< \brief Mode fault detection. */
    60. 

  60. #define SPI_LLB         0x00000080  /*!< \brief Local loopback enable. */
    61. 

  61. #define SPI_PCS         0x000F0000  /*!< \brief Peripheral chip select mask. */
    62. 

  62. #define SPI_PCS_0       0x000E0000  /*!< \brief Peripheral chip select 0. */
    63. 

  63. #define SPI_PCS_1       0x000D0000  /*!< \brief Peripheral chip select 1. */
    64. 

  64. #define SPI_PCS_2       0x000B0000  /*!< \brief Peripheral chip select 2. */
    65. 

  65. #define SPI_PCS_3       0x00070000  /*!< \brief Peripheral chip select 3. */
    66. 

  66. #define SPI_PCS_LSB             16  /*!< \brief Least significant bit of peripheral chip select. */
    67. 

  67. #define SPI_DLYBCS      0xFF000000  /*!< \brief Mask for delay between chip selects. */
    68. 

  68. #define SPI_DLYBCS_LSB          24  /*!< \brief Least significant bit of delay between chip selects. */
    69. 

  69. /*@}*/
    70. 

  70. 

  71. /*! \name SPI Receive Data Register */
    72. 

  72. /*@{*/
    73. 

  73. #define SPI_RDR_OFF		0x00000008  /*!< \brief Receive data register offset. */
    74. 

  74. 

  75. #define SPI_RD          0x0000FFFF  /*!< \brief Receive data mask. */
    76. 

  76. #define SPI_RD_LSB              0   /*!< \brief Least significant bit of receive data. */
    77. 

  77. /*@}*/
    78. 

  78. 

  79. /*! \name SPI Transmit Data Register */
    80. 

  80. /*@{*/
    81. 

  81. #define SPI_TDR_OFF		0x0000000C  /*!< \brief Transmit data register offset. */
    82. 

  82. 

  83. #define SPI_TD          0x0000FFFF  /*!< \brief Transmit data mask. */
    84. 

  84. #define SPI_TD_LSB              0   /*!< \brief Least significant bit of transmit data. */
    85. 

  85. /*@}*/
    86. 

  86. 

  87. /*! \name SPI Status and Interrupt Register */
    88. 

  88. /*@{*/
    89. 

  89. #define SPI_SR_OFF		0x00000010  /*!< \brief Status register offset. */
    90. 

  90. #define SPI_IER_OFF		0x00000014  /*!< \brief Interrupt enable register offset. */
    91. 

  91. #define SPI_IDR_OFF		0x00000018  /*!< \brief Interrupt disable register offset. */
    92. 

  92. #define SPI_IMR_OFF		0x0000001C  /*!< \brief Interrupt mask register offset. */
    93. 

  93. 

  94. #define SPI_RDRF        0x00000001  /*!< \brief Receive data register full. */
    95. 

  95. #define SPI_TDRE        0x00000002  /*!< \brief Transmit data register empty. */
    96. 

  96. #define SPI_MODF        0x00000004  /*!< \brief Mode fault error. */
    97. 

  97. #define SPI_OVRES       0x00000008  /*!< \brief Overrun error status. */
    98. 

  98. #define SPI_ENDRX       0x00000010  /*!< \brief End of RX buffer. */
    99. 

  99. #define SPI_ENDTX       0x00000020  /*!< \brief End of TX buffer. */
    100. 

  100. #define SPI_RXBUFF      0x00000040  /*!< \brief RX buffer full. */
    101. 

  101. #define SPI_TXBUFE      0x00000080  /*!< \brief TX buffer empty. */
    102. 

  102. #define SPI_NSSR        0x00000100  /*!< \brief NSS rising. */
    103. 

  103. #define SPI_TXEMPTY     0x00000200  /*!< \brief Transmission register empty. */
    104. 

  104. #define SPI_SPIENS      0x00010000  /*!< \brief SPI enable status. */
    105. 

  105. /*@}*/
    106. 

  106. 

  107. /*! \name SPI Chip Select Registers */
    108. 

  108. /*@{*/
    109. 

  109. #define SPI_CSR0_OFF	0x00000030  /*!< \brief Chip select register 0 offset. */
    110. 

  110. #define SPI_CSR1_OFF	0x00000034  /*!< \brief Chip select register 1 offset. */
    111. 

  111. #define SPI_CSR2_OFF	0x00000038  /*!< \brief Chip select register 2 offset. */
    112. 

  112. #define SPI_CSR3_OFF    0x0000003C  /*!< \brief Chip select register 3 offset. */
    113. 

  113. 

  114. #define SPI_CPOL        0x00000001  /*!< \brief Clock polarity. */
    115. 

  115. #define SPI_NCPHA       0x00000002  /*!< \brief Clock phase. */
    116. 

  116. #define SPI_CSAAT       0x00000008  /*!< \brief Chip select active after transfer. */
    117. 

  117. #define SPI_BITS        0x000000F0  /*!< \brief Bits per transfer mask. */
    118. 

  118. #define SPI_BITS_8      0x00000000  /*!< \brief 8 bits per transfer. */
    119. 

  119. #define SPI_BITS_9      0x00000010  /*!< \brief 9 bits per transfer. */
    120. 

  120. #define SPI_BITS_10     0x00000020  /*!< \brief 10 bits per transfer. */
    121. 

  121. #define SPI_BITS_11     0x00000030  /*!< \brief 11 bits per transfer. */
    122. 

  122. #define SPI_BITS_12     0x00000040  /*!< \brief 12 bits per transfer. */
    123. 

  123. #define SPI_BITS_13     0x00000050  /*!< \brief 13 bits per transfer. */
    124. 

  124. #define SPI_BITS_14     0x00000060  /*!< \brief 14 bits per transfer. */
    125. 

  125. #define SPI_BITS_15     0x00000070  /*!< \brief 15 bits per transfer. */
    126. 

  126. #define SPI_BITS_16     0x00000080  /*!< \brief 16 bits per transfer. */
    127. 

  127. #define SPI_BITS_LSB            4   /*!< \brief Least significant bit of bits per transfer. */
    128. 

  128. #define SPI_SCBR        0x0000FF00  /*!< \brief Serial clock baud rate mask. */
    129. 

  129. #define SPI_SCBR_LSB            8   /*!< \brief Least significant bit of serial clock baud rate. */
    130. 

  130. #define SPI_DLYBS       0x00FF0000  /*!< \brief Delay before SPCK mask. */
    131. 

  131. #define SPI_DLYBS_LSB           16  /*!< \brief Least significant bit of delay before SPCK. */
    132. 

  132. #define SPI_DLYBCT      0xFF000000  /*!< \brief Delay between consecutive transfers mask. */
    133. 

  133. #define SPI_DLYBCT_LSB          24  /*!< \brief Least significant bit of delay between consecutive transfers. */
    134. 

  134. /*@}*/
    135. 

  135. 

  136. /*! \name Single SPI Register Addresses */
    137. 

  137. /*@{*/
    138. 

  138. #if defined(SPI_BASE)
    139. 

  139. #define SPI0_BASE   SPI_BASE
    140. 

  140. #define	SPI_CR		SPI0_CR     /*!< \brief SPI Control Register Write-only. */
    141. 

  141. #define SPI_MR		SPI0_MR     /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
    142. 

  142. #define SPI_RDR		SPI0_RDR    /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
    143. 

  143. #define SPI_TDR		SPI0_TDR    /*!< \brief SPI Transmit Data Register Write-only . */
    144. 

  144. #define SPI_SR		SPI0_SR     /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
    145. 

  145. #define SPI_IER		SPI0_IER    /*!< \brief SPI Interrupt Enable Register Write-only. */
    146. 

  146. #define SPI_IDR		SPI0_IDR    /*!< \brief SPI Interrupt Disable Register Write-only. */
    147. 

  147. #define SPI_IMR		SPI0_IMR    /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
    148. 

  148. #define SPI_CSR0	SPI0_CSR0   /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
    149. 

  149. #define SPI_CSR1	SPI0_CSR1   /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
    150. 

  150. #define SPI_CSR2	SPI0_CSR2   /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
    151. 

  151. #define SPI_CSR3	SPI0_CSR3   /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
    152. 

  152. #if defined(SPI_HAS_PDC)
    153. 

  153. #define SPI_RPR     SPI0_RPR    /*!< \brief PDC channel 0 receive pointer register. */
    154. 

  154. #define SPI_RCR     SPI0_RCR    /*!< \brief PDC channel 0 receive counter register. */
    155. 

  155. #define SPI_TPR     SPI0_TPR    /*!< \brief PDC channel 0 transmit pointer register. */
    156. 

  156. #define SPI_TCR     SPI0_TCR    /*!< \brief PDC channel 0 transmit counter register. */
    157. 

  157. #define SPI_RNPR    SPI0_RNPR   /*!< \brief PDC channel 0 receive next pointer register. */
    158. 

  158. #define SPI_RNCR    SPI0_RNCR   /*!< \brief PDC channel 0 receive next counter register. */
    159. 

  159. #define SPI_TNPR    SPI0_TNPR   /*!< \brief PDC channel 0 transmit next pointer register. */
    160. 

  160. #define SPI_TNCR    SPI0_TNCR   /*!< \brief PDC channel 0 transmit next counter register. */
    161. 

  161. #define SPI_PTCR    SPI0_PTCR   /*!< \brief PDC channel 0 transfer control register. */
    162. 

  162. #define SPI_PTSR    SPI0_PTSR   /*!< \brief PDC channel 0 transfer status register. */
    163. 

  163. #endif /* SPI_HAS_PDC */
    164. 

  164. #endif /* SPI_BASE */
    165. 

  165. /*@}*/
    166. 

  166. 

  167. /*! \name SPI 0 Register Addresses */
    168. 

  168. /*@{*/
    169. 

  169. #if defined(SPI0_BASE)
    170. 

  170. #define	SPI0_CR		(SPI0_BASE + SPI_CR_OFF)        /*!< \brief SPI Control Register Write-only. */
    171. 

  171. #define SPI0_MR		(SPI0_BASE + SPI_MR_OFF)        /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
    172. 

  172. #define SPI0_RDR	(SPI0_BASE + SPI_RDR_OFF)       /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
    173. 

  173. #define SPI0_TDR	(SPI0_BASE + SPI_TDR_OFF)       /*!< \brief SPI Transmit Data Register Write-only . */
    174. 

  174. #define SPI0_SR		(SPI0_BASE + SPI_SR_OFF)        /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
    175. 

  175. #define SPI0_IER	(SPI0_BASE + SPI_IER_OFF)       /*!< \brief SPI Interrupt Enable Register Write-only. */
    176. 

  176. #define SPI0_IDR	(SPI0_BASE + SPI_IDR_OFF)       /*!< \brief SPI Interrupt Disable Register Write-only. */
    177. 

  177. #define SPI0_IMR	(SPI0_BASE + SPI_IMR_OFF)       /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
    178. 

  178. #define SPI0_CSR0	(SPI0_BASE + SPI_CSR0_OFF)      /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
    179. 

  179. #define SPI0_CSR1	(SPI0_BASE + SPI_CSR1_OFF)      /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
    180. 

  180. #define SPI0_CSR2	(SPI0_BASE + SPI_CSR2_OFF)      /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
    181. 

  181. #define SPI0_CSR3	(SPI0_BASE + SPI_CSR3_OFF)      /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
    182. 

  182. #if defined(SPI_HAS_PDC)
    183. 

  183. #define SPI0_RPR    (SPI0_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC channel 0 receive pointer register. */
    184. 

  184. #define SPI0_RCR    (SPI0_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC channel 0 receive counter register. */
    185. 

  185. #define SPI0_TPR    (SPI0_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC channel 0 transmit pointer register. */
    186. 

  186. #define SPI0_TCR    (SPI0_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC channel 0 transmit counter register. */
    187. 

  187. #define SPI0_RNPR   (SPI0_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC channel 0 receive next pointer register. */
    188. 

  188. #define SPI0_RNCR   (SPI0_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC channel 0 receive next counter register. */
    189. 

  189. #define SPI0_TNPR   (SPI0_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC channel 0 transmit next pointer register. */
    190. 

  190. #define SPI0_TNCR   (SPI0_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC channel 0 transmit next counter register. */
    191. 

  191. #define SPI0_PTCR   (SPI0_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC channel 0 transfer control register. */
    192. 

  192. #define SPI0_PTSR   (SPI0_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC channel 0 transfer status register. */
    193. 

  193. #endif /* SPI_HAS_PDC */
    194. 

  194. #endif /* SPI0_BASE */
    195. 

  195. /*@}*/
    196. 

  196. 

  197. /*! \name SPI 1 Register Addresses */
    198. 

  198. /*@{*/
    199. 

  199. #if defined(SPI1_BASE)
    200. 

  200. #define	SPI1_CR		(SPI1_BASE + SPI_CR_OFF)        /*!< \brief SPI Control Register Write-only. */
    201. 

  201. #define SPI1_MR		(SPI1_BASE + SPI_MR_OFF)        /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
    202. 

  202. #define SPI1_RDR	(SPI1_BASE + SPI_RDR_OFF)       /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
    203. 

  203. #define SPI1_TDR	(SPI1_BASE + SPI_TDR_OFF)       /*!< \brief SPI Transmit Data Register Write-only . */
    204. 

  204. #define SPI1_SR		(SPI1_BASE + SPI_SR_OFF)        /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
    205. 

  205. #define SPI1_IER	(SPI1_BASE + SPI_IER_OFF)       /*!< \brief SPI Interrupt Enable Register Write-only. */
    206. 

  206. #define SPI1_IDR	(SPI1_BASE + SPI_IDR_OFF)       /*!< \brief SPI Interrupt Disable Register Write-only. */
    207. 

  207. #define SPI1_IMR	(SPI1_BASE + SPI_IMR_OFF)       /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
    208. 

  208. #define SPI1_CSR0	(SPI1_BASE + SPI_CSR0_OFF)      /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
    209. 

  209. #define SPI1_CSR1	(SPI1_BASE + SPI_CSR1_OFF)      /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
    210. 

  210. #define SPI1_CSR2	(SPI1_BASE + SPI_CSR2_OFF)      /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
    211. 

  211. #define SPI1_CSR3	(SPI1_BASE + SPI_CSR3_OFF)      /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
    212. 

  212. #if defined(SPI_HAS_PDC)
    213. 

  213. #define SPI1_RPR    (SPI1_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC channel 1 receive pointer register. */
    214. 

  214. #define SPI1_RCR    (SPI1_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC channel 1 receive counter register. */
    215. 

  215. #define SPI1_TPR    (SPI1_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC channel 1 transmit pointer register. */
    216. 

  216. #define SPI1_TCR    (SPI1_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC channel 1 transmit counter register. */
    217. 

  217. #define SPI1_RNPR   (SPI1_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC channel 1 receive next pointer register. */
    218. 

  218. #define SPI1_RNCR   (SPI1_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC channel 1 receive next counter register. */
    219. 

  219. #define SPI1_TNPR   (SPI1_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC channel 1 transmit next pointer register. */
    220. 

  220. #define SPI1_TNCR   (SPI1_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC channel 1 transmit next counter register. */
    221. 

  221. #define SPI1_PTCR   (SPI1_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC channel 1 transfer control register. */
    222. 

  222. #define SPI1_PTSR   (SPI1_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC channel 1 transfer status register. */
    223. 

  223. #endif /* SPI_HAS_PDC */
    224. 

  224. #endif /* SPI1_BASE */
    225. 

  225. /*@}*/
    226. 

  226. 

  227. /*@} xgNutArchArmAt91Spi */
    228. 

  228. 

  229. #endif  /* _ARCH_ARM_AT91_SPI_H_ */
    230.