at91_dbg1.c 4.5 KB

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  1. /*
  2. * Copyright (C) 2001-2006 by egnite Software GmbH
  3. * Copyright (C) 2010 by egnite GmbH
  4. *
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. *
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions and the following disclaimer.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. Neither the name of the copyright holders nor the names of
  17. * contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  23. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  24. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  26. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  27. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  28. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  30. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31. * SUCH DAMAGE.
  32. *
  33. * For additional information see http://www.ethernut.de/
  34. */
  35. /*!
  36. * \file arch/arm/dev/at91_dbg1.c
  37. * \brief AT91 debug output device using USART1.
  38. *
  39. * \verbatim
  40. * $Id$
  41. * \endverbatim
  42. */
  43. #include <cfg/uart.h>
  44. #include <arch/arm/atmel/debug_at91.h>
  45. #if defined(USART1_BASE)
  46. /*!
  47. * \addtogroup xgDevDebugAt91
  48. */
  49. /*@{*/
  50. #ifndef NUT_DEV_DEBUG_SPEED
  51. #ifdef UART1_INIT_BAUDRATE
  52. #define NUT_DEV_DEBUG_SPEED UART1_INIT_BAUDRATE
  53. #else
  54. #define NUT_DEV_DEBUG_SPEED 115200
  55. #endif
  56. #endif
  57. /*!
  58. * \brief Initialize debug device 1.
  59. *
  60. * \return Always 0.
  61. */
  62. static int Debug1Init(NUTDEVICE * dev)
  63. {
  64. /* Enable UART clock. */
  65. #if defined (PS_PCER)
  66. outr(PS_PCER, _BV(US1_ID));
  67. #elif defined (PMC_PCER)
  68. outr(PMC_PCER, _BV(US1_ID));
  69. #endif
  70. /* Disable GPIO on UART tx/rx pins. */
  71. #if defined (P22_RXD1) && defined (P21_TXD1)
  72. outr(PIO_PDR, _BV(P22_RXD1) | _BV(P21_TXD1));
  73. #elif defined (PA5_RXD1_A) && defined (PA6_TXD1_A)
  74. outr(PIOA_PDR, _BV(PA5_RXD1_A) | _BV(PA6_TXD1_A));
  75. #elif defined (PA21_RXD1_A) && defined (PA22_TXD1_A)
  76. outr(PIOA_PDR, _BV(PA21_RXD1_A) | _BV(PA22_TXD1_A));
  77. #endif
  78. /* Reset UART. */
  79. outr(US1_CR, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
  80. /* Disable all UART interrupts. */
  81. outr(US1_IDR, 0xFFFFFFFF);
  82. #if defined (US1_RCR) && defined(US1_TCR)
  83. /* Clear UART counter registers. */
  84. outr(US1_RCR, 0);
  85. outr(US1_TCR, 0);
  86. #endif
  87. #if NUT_DEV_DEBUG_SPEED
  88. /* Set UART baud rate generator register. */
  89. outr(US1_BRGR, At91BaudRateDiv(NUT_DEV_DEBUG_SPEED));
  90. #endif
  91. /* Set UART mode to 8 data bits, no parity and 1 stop bit. */
  92. outr(US1_MR, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
  93. /* Enable UART receiver and transmitter. */
  94. outr(US1_CR, US_RXEN | US_TXEN);
  95. return 0;
  96. }
  97. static NUTFILE dbgfile1;
  98. /*!
  99. * \brief Debug device 1 information structure.
  100. */
  101. NUTDEVICE devDebug1 = {
  102. 0, /*!< Pointer to next device, dev_next. */
  103. {'u', 'a', 'r', 't', '1', 0, 0, 0, 0}
  104. , /*!< Unique device name, dev_name. */
  105. 0, /*!< Type of device, dev_type. */
  106. USART1_BASE, /*!< Base address, dev_base. */
  107. 0, /*!< First interrupt number, dev_irq. */
  108. 0, /*!< Interface control block, dev_icb. */
  109. &dbgfile1, /*!< Driver control block, dev_dcb. */
  110. Debug1Init, /*!< Driver initialization routine, dev_init. */
  111. At91DevDebugIOCtl, /*!< Driver specific control function, dev_ioctl. */
  112. 0, /*!< dev_read. */
  113. At91DevDebugWrite, /*!< dev_write. */
  114. At91DevDebugOpen, /*!< dev_opem. */
  115. At91DevDebugClose, /*!< dev_close. */
  116. 0, /*!< dev_size. */
  117. 0 /*!< dev_select, optional, not yet implemented */
  118. };
  119. #endif /* USART1_BASE */
  120. /*@}*/