ih_at91pioc.c 5.3 KB

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  1. /*
  2. * Copyright (C) 2005-2007 by egnite Software GmbH. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * 3. Neither the name of the copyright holders nor the names of
  14. * contributors may be used to endorse or promote products derived
  15. * from this software without specific prior written permission.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  21. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28. * SUCH DAMAGE.
  29. *
  30. * For additional information see http://www.ethernut.de/
  31. *
  32. */
  33. /*
  34. * $Id: ih_at91pioc.c 4937 2013-01-22 11:38:42Z haraldkipp $
  35. */
  36. #include <arch/arm.h>
  37. #include <dev/irqreg.h>
  38. #if defined(PIOC_ID)
  39. #ifndef NUT_IRQPRI_PIOC
  40. #define NUT_IRQPRI_PIOC 4
  41. #endif
  42. static int PortIoIrqCtl(int cmd, void *param);
  43. IRQ_HANDLER sig_PIOC = {
  44. #ifdef NUT_PERFMON
  45. 0, /* Interrupt counter, ir_count. */
  46. #endif
  47. NULL, /* Passed argument, ir_arg. */
  48. NULL, /* Handler subroutine, ir_handler. */
  49. PortIoIrqCtl /* Interrupt control, ir_ctl. */
  50. };
  51. /*!
  52. * \brief Port I/O interrupt entry.
  53. */
  54. static void PortIoIrqEntry(void) NUT_NAKED_FUNC;
  55. void PortIoIrqEntry(void)
  56. {
  57. IRQ_ENTRY();
  58. #ifdef NUT_PERFMON
  59. sig_PIOC.ir_count++;
  60. #endif
  61. if (sig_PIOC.ir_handler) {
  62. (sig_PIOC.ir_handler) (sig_PIOC.ir_arg);
  63. }
  64. IRQ_EXIT();
  65. }
  66. /*!
  67. * \brief Port I/O interrupt control.
  68. *
  69. * \param cmd Control command.
  70. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  71. * - NUT_IRQCTL_STATUS Query interrupt status.
  72. * - NUT_IRQCTL_ENABLE Enable interrupt.
  73. * - NUT_IRQCTL_DISABLE Disable interrupt.
  74. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  75. * - NUT_IRQCTL_SETMODE Set interrupt mode (NUT_IRQMODE_LEVEL or NUT_IRQMODE_EDGE).
  76. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  77. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  78. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  79. * \param param Pointer to optional parameter.
  80. *
  81. * \return 0 on success, -1 otherwise.
  82. */
  83. static int PortIoIrqCtl(int cmd, void *param)
  84. {
  85. int rc = 0;
  86. unsigned int *ival = (unsigned int *)param;
  87. int_fast8_t enabled = inr(AIC_IMR) & _BV(PIOC_ID);
  88. /* Disable interrupt. */
  89. if (enabled) {
  90. outr(AIC_IDCR, _BV(PIOC_ID));
  91. }
  92. switch(cmd) {
  93. case NUT_IRQCTL_INIT:
  94. /* Set the vector. */
  95. outr(AIC_SVR(PIOC_ID), (unsigned int)PortIoIrqEntry);
  96. /* Initialize to edge triggered with defined priority. */
  97. outr(AIC_SMR(PIOC_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_PIOC);
  98. /* Clear interrupt */
  99. outr(AIC_ICCR, _BV(PIOC_ID));
  100. break;
  101. case NUT_IRQCTL_STATUS:
  102. if (enabled) {
  103. *ival |= 1;
  104. }
  105. else {
  106. *ival &= ~1;
  107. }
  108. break;
  109. case NUT_IRQCTL_ENABLE:
  110. enabled = 1;
  111. break;
  112. case NUT_IRQCTL_DISABLE:
  113. enabled = 0;
  114. break;
  115. case NUT_IRQCTL_GETMODE:
  116. {
  117. unsigned int val = inr(AIC_SMR(PIOC_ID)) & AIC_SRCTYPE;
  118. if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
  119. *ival = NUT_IRQMODE_LEVEL;
  120. } else {
  121. *ival = NUT_IRQMODE_EDGE;
  122. }
  123. }
  124. break;
  125. case NUT_IRQCTL_SETMODE:
  126. if (*ival == NUT_IRQMODE_LEVEL) {
  127. outr(AIC_SMR(PIOC_ID), (inr(AIC_SMR(PIOC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
  128. } else if (*ival == NUT_IRQMODE_EDGE) {
  129. outr(AIC_SMR(PIOC_ID), (inr(AIC_SMR(PIOC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
  130. } else {
  131. rc = -1;
  132. }
  133. break;
  134. case NUT_IRQCTL_GETPRIO:
  135. *ival = inr(AIC_SMR(PIOC_ID)) & AIC_PRIOR;
  136. break;
  137. case NUT_IRQCTL_SETPRIO:
  138. outr(AIC_SMR(PIOC_ID), (inr(AIC_SMR(PIOC_ID)) & ~AIC_PRIOR) | *ival);
  139. break;
  140. #ifdef NUT_PERFMON
  141. case NUT_IRQCTL_GETCOUNT:
  142. *ival = (unsigned int)sig_PIOC.ir_count;
  143. sig_PIOC.ir_count = 0;
  144. break;
  145. #endif
  146. default:
  147. rc = -1;
  148. break;
  149. }
  150. /* Enable interrupt. */
  151. if (enabled) {
  152. outr(AIC_IECR, _BV(PIOC_ID));
  153. }
  154. return rc;
  155. }
  156. #endif /* PIOC_ID */