ih_at91tc0.c 5.9 KB

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  1. /*
  2. * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * 3. Neither the name of the copyright holders nor the names of
  14. * contributors may be used to endorse or promote products derived
  15. * from this software without specific prior written permission.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  21. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28. * SUCH DAMAGE.
  29. *
  30. * For additional information see http://www.ethernut.de/
  31. *
  32. */
  33. /*
  34. * $Log$
  35. * Revision 1.5 2008/08/11 06:59:11 haraldkipp
  36. * BSD types replaced by stdint types (feature request #1282721).
  37. *
  38. * Revision 1.4 2008/07/26 09:43:01 haraldkipp
  39. * Added support for retrieving and setting the interrupt mode.
  40. *
  41. * Revision 1.3 2006/09/29 12:36:48 haraldkipp
  42. * Default interrupt priority changed from 4 to 0. As this is typically used
  43. * by the system timer, lowest priority is fine.
  44. *
  45. * Revision 1.2 2006/06/28 17:10:27 haraldkipp
  46. * Include more general header file for ARM.
  47. *
  48. * Revision 1.1 2005/10/24 08:56:09 haraldkipp
  49. * First check in.
  50. *
  51. */
  52. #include <arch/arm.h>
  53. #include <dev/irqreg.h>
  54. #ifndef NUT_IRQPRI_TC0
  55. #define NUT_IRQPRI_TC0 0
  56. #endif
  57. static int TimerCounter0IrqCtl(int cmd, void *param);
  58. IRQ_HANDLER sig_TC0 = {
  59. #ifdef NUT_PERFMON
  60. 0, /* Interrupt counter, ir_count. */
  61. #endif
  62. NULL, /* Passed argument, ir_arg. */
  63. NULL, /* Handler subroutine, ir_handler. */
  64. TimerCounter0IrqCtl /* Interrupt control, ir_ctl. */
  65. };
  66. /*!
  67. * \brief Timer/Counter 0 interrupt entry.
  68. */
  69. static unsigned int dummy;
  70. static void TimerCounter0IrqEntry(void) NUT_NAKED_FUNC;
  71. void TimerCounter0IrqEntry(void)
  72. {
  73. IRQ_ENTRY();
  74. #ifdef NUT_PERFMON
  75. sig_TC0.ir_count++;
  76. #endif
  77. dummy = inr(TC0_SR);
  78. if (sig_TC0.ir_handler) {
  79. (sig_TC0.ir_handler) (sig_TC0.ir_arg);
  80. }
  81. IRQ_EXIT();
  82. }
  83. /*!
  84. * \brief Timer/Counter 0 interrupt control.
  85. *
  86. * \param cmd Control command.
  87. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  88. * - NUT_IRQCTL_STATUS Query interrupt status.
  89. * - NUT_IRQCTL_ENABLE Enable interrupt.
  90. * - NUT_IRQCTL_DISABLE Disable interrupt.
  91. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  92. * - NUT_IRQCTL_SETMODE Set interrupt mode (NUT_IRQMODE_LEVEL or NUT_IRQMODE_EDGE).
  93. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  94. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  95. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  96. * \param param Pointer to optional parameter.
  97. *
  98. * \return 0 on success, -1 otherwise.
  99. */
  100. static int TimerCounter0IrqCtl(int cmd, void *param)
  101. {
  102. int rc = 0;
  103. unsigned int *ival = (unsigned int *)param;
  104. int_fast8_t enabled = inr(AIC_IMR) & _BV(TC0_ID);
  105. /* Disable interrupt. */
  106. if (enabled) {
  107. outr(AIC_IDCR, _BV(TC0_ID));
  108. }
  109. switch(cmd) {
  110. case NUT_IRQCTL_INIT:
  111. /* Set the vector. */
  112. outr(AIC_SVR(TC0_ID), (unsigned int)TimerCounter0IrqEntry);
  113. /* Initialize to edge triggered with defined priority. */
  114. outr(AIC_SMR(TC0_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC0);
  115. /* Clear interrupt */
  116. outr(AIC_ICCR, _BV(TC0_ID));
  117. break;
  118. case NUT_IRQCTL_STATUS:
  119. if (enabled) {
  120. *ival |= 1;
  121. }
  122. else {
  123. *ival &= ~1;
  124. }
  125. break;
  126. case NUT_IRQCTL_ENABLE:
  127. enabled = 1;
  128. break;
  129. case NUT_IRQCTL_DISABLE:
  130. enabled = 0;
  131. break;
  132. case NUT_IRQCTL_GETMODE:
  133. {
  134. unsigned int val = inr(AIC_SMR(TC0_ID)) & AIC_SRCTYPE;
  135. if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
  136. *ival = NUT_IRQMODE_LEVEL;
  137. } else {
  138. *ival = NUT_IRQMODE_EDGE;
  139. }
  140. }
  141. break;
  142. case NUT_IRQCTL_SETMODE:
  143. if (*ival == NUT_IRQMODE_LEVEL) {
  144. outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
  145. } else if (*ival == NUT_IRQMODE_EDGE) {
  146. outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
  147. } else {
  148. rc = -1;
  149. }
  150. break;
  151. case NUT_IRQCTL_GETPRIO:
  152. *ival = inr(AIC_SMR(TC0_ID)) & AIC_PRIOR;
  153. break;
  154. case NUT_IRQCTL_SETPRIO:
  155. outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_PRIOR) | *ival);
  156. break;
  157. #ifdef NUT_PERFMON
  158. case NUT_IRQCTL_GETCOUNT:
  159. *ival = (unsigned int)sig_TC0.ir_count;
  160. sig_TC0.ir_count = 0;
  161. break;
  162. #endif
  163. default:
  164. rc = -1;
  165. break;
  166. }
  167. /* Enable interrupt. */
  168. if (enabled) {
  169. outr(AIC_IECR, _BV(TC0_ID));
  170. }
  171. return rc;
  172. }