ih_at91uart1.c 5.7 KB

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  1. /*
  2. * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * 3. Neither the name of the copyright holders nor the names of
  14. * contributors may be used to endorse or promote products derived
  15. * from this software without specific prior written permission.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  21. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28. * SUCH DAMAGE.
  29. *
  30. * For additional information see http://www.ethernut.de/
  31. *
  32. */
  33. /*
  34. * $Log$
  35. * Revision 1.4 2008/08/11 06:59:12 haraldkipp
  36. * BSD types replaced by stdint types (feature request #1282721).
  37. *
  38. * Revision 1.3 2008/07/26 09:42:21 haraldkipp
  39. * Use level sensitive interrupts by default.
  40. * Added support for retrieving and setting the interrupt mode.
  41. *
  42. * Revision 1.2 2006/06/28 17:10:27 haraldkipp
  43. * Include more general header file for ARM.
  44. *
  45. * Revision 1.1 2005/10/24 08:56:09 haraldkipp
  46. * First check in.
  47. *
  48. */
  49. #include <arch/arm.h>
  50. #include <dev/irqreg.h>
  51. #ifndef NUT_IRQPRI_UART1
  52. #define NUT_IRQPRI_UART1 4
  53. #endif
  54. static int Uart1IrqCtl(int cmd, void *param);
  55. IRQ_HANDLER sig_UART1 = {
  56. #ifdef NUT_PERFMON
  57. 0, /* Interrupt counter, ir_count. */
  58. #endif
  59. NULL, /* Passed argument, ir_arg. */
  60. NULL, /* Handler subroutine, ir_handler. */
  61. Uart1IrqCtl /* Interrupt control, ir_ctl. */
  62. };
  63. /*!
  64. * \brief UART 1 interrupt entry.
  65. */
  66. static void Uart1IrqEntry(void) NUT_NAKED_FUNC;
  67. void Uart1IrqEntry(void)
  68. {
  69. IRQ_ENTRY();
  70. #ifdef NUT_PERFMON
  71. sig_UART1.ir_count++;
  72. #endif
  73. if (sig_UART1.ir_handler) {
  74. (sig_UART1.ir_handler) (sig_UART1.ir_arg);
  75. }
  76. IRQ_EXIT();
  77. }
  78. /*!
  79. * \brief UART 1 interrupt control.
  80. *
  81. * \param cmd Control command.
  82. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  83. * - NUT_IRQCTL_STATUS Query interrupt status.
  84. * - NUT_IRQCTL_ENABLE Enable interrupt.
  85. * - NUT_IRQCTL_DISABLE Disable interrupt.
  86. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  87. * - NUT_IRQCTL_SETMODE Set interrupt mode (NUT_IRQMODE_LEVEL or NUT_IRQMODE_EDGE).
  88. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  89. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  90. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  91. * \param param Pointer to optional parameter.
  92. *
  93. * \return 0 on success, -1 otherwise.
  94. */
  95. static int Uart1IrqCtl(int cmd, void *param)
  96. {
  97. int rc = 0;
  98. unsigned int *ival = (unsigned int *)param;
  99. int_fast8_t enabled = inr(AIC_IMR) & _BV(US1_ID);
  100. /* Disable interrupt. */
  101. if (enabled) {
  102. outr(AIC_IDCR, _BV(US1_ID));
  103. }
  104. switch(cmd) {
  105. case NUT_IRQCTL_INIT:
  106. /* Set the vector. */
  107. outr(AIC_SVR(US1_ID), (unsigned int)Uart1IrqEntry);
  108. /* Initialize to edge triggered with defined priority. */
  109. outr(AIC_SMR(US1_ID), AIC_SRCTYPE_INT_LEVEL_SENSITIVE | NUT_IRQPRI_UART1);
  110. /* Clear interrupt */
  111. outr(AIC_ICCR, _BV(US1_ID));
  112. break;
  113. case NUT_IRQCTL_STATUS:
  114. if (enabled) {
  115. *ival |= 1;
  116. }
  117. else {
  118. *ival &= ~1;
  119. }
  120. break;
  121. case NUT_IRQCTL_ENABLE:
  122. enabled = 1;
  123. break;
  124. case NUT_IRQCTL_DISABLE:
  125. enabled = 0;
  126. break;
  127. case NUT_IRQCTL_GETMODE:
  128. {
  129. unsigned int val = inr(AIC_SMR(US1_ID)) & AIC_SRCTYPE;
  130. if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
  131. *ival = NUT_IRQMODE_LEVEL;
  132. } else {
  133. *ival = NUT_IRQMODE_EDGE;
  134. }
  135. }
  136. break;
  137. case NUT_IRQCTL_SETMODE:
  138. if (*ival == NUT_IRQMODE_LEVEL) {
  139. outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
  140. } else if (*ival == NUT_IRQMODE_EDGE) {
  141. outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
  142. } else {
  143. rc = -1;
  144. }
  145. break;
  146. case NUT_IRQCTL_GETPRIO:
  147. *ival = inr(AIC_SMR(US1_ID)) & AIC_PRIOR;
  148. break;
  149. case NUT_IRQCTL_SETPRIO:
  150. outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_PRIOR) | *ival);
  151. break;
  152. #ifdef NUT_PERFMON
  153. case NUT_IRQCTL_GETCOUNT:
  154. *ival = (unsigned int)sig_UART1.ir_count;
  155. sig_UART1.ir_count = 0;
  156. break;
  157. #endif
  158. default:
  159. rc = -1;
  160. break;
  161. }
  162. /* Enable interrupt. */
  163. if (enabled) {
  164. outr(AIC_IECR, _BV(US1_ID));
  165. }
  166. return rc;
  167. }