ih_int5.c 5.2 KB

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  1. /*
  2. * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * 3. Neither the name of the copyright holders nor the names of
  14. * contributors may be used to endorse or promote products derived
  15. * from this software without specific prior written permission.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  21. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28. * SUCH DAMAGE.
  29. *
  30. * For additional information see http://www.ethernut.de/
  31. *
  32. */
  33. /*!
  34. * \file arch/avr/dev/ih_int5.c
  35. * \brief AVR external interrupt 5.
  36. *
  37. * \verbatim
  38. * $Id: ih_int5.c 4706 2012-10-06 17:42:01Z haraldkipp $
  39. * \endverbatim
  40. */
  41. #include <dev/irqreg.h>
  42. /*!
  43. * \addtogroup xgIrqReg
  44. */
  45. /*@{*/
  46. static int AvrInterrupt5Ctl(int cmd, void *param);
  47. IRQ_HANDLER sig_INTERRUPT5 = {
  48. #ifdef NUT_PERFMON
  49. 0, /* Interrupt counter, ir_count. */
  50. #endif
  51. NULL, /* Passed argument, ir_arg. */
  52. NULL, /* Handler subroutine, ir_handler. */
  53. AvrInterrupt5Ctl /* Interrupt control, ir_ctl. */
  54. };
  55. /*!
  56. * \brief External interrupt 5 control.
  57. *
  58. * \param cmd Control command.
  59. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  60. * - NUT_IRQCTL_STATUS Query interrupt status.
  61. * - NUT_IRQCTL_ENABLE Enable interrupt.
  62. * - NUT_IRQCTL_DISABLE Disable interrupt.
  63. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  64. * - NUT_IRQCTL_SETMODE Set interrupt mode.
  65. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  66. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  67. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  68. * \param param Pointer to optional parameter.
  69. *
  70. * \return 0 on success, -1 otherwise.
  71. */
  72. static int AvrInterrupt5Ctl(int cmd, void *param)
  73. {
  74. int rc = 0;
  75. unsigned int *ival = (unsigned int *) param;
  76. int_fast8_t enabled = bit_is_set(EIMSK, INT5);
  77. uint8_t bval;
  78. /* Disable interrupt. */
  79. cbi(EIMSK, INT5);
  80. switch (cmd) {
  81. case NUT_IRQCTL_INIT:
  82. /* Initialize to low level triggered. */
  83. cbi(EICR, ISC50);
  84. cbi(EICR, ISC51);
  85. case NUT_IRQCTL_CLEAR:
  86. /* Clear any pending interrupt. */
  87. outb(EIFR, _BV(INTF5));
  88. break;
  89. case NUT_IRQCTL_STATUS:
  90. if (bit_is_set(EIFR, INTF5)) {
  91. *ival = 1;
  92. } else {
  93. *ival = 0;
  94. }
  95. if (enabled) {
  96. *ival |= 0x80;
  97. }
  98. break;
  99. case NUT_IRQCTL_ENABLE:
  100. enabled = 1;
  101. break;
  102. case NUT_IRQCTL_DISABLE:
  103. enabled = 0;
  104. break;
  105. case NUT_IRQCTL_GETMODE:
  106. bval = inb(EICR) & _BV(ISC51 | ISC50);
  107. if (bval == _BV(ISC51)) {
  108. *ival = NUT_IRQMODE_FALLINGEDGE;
  109. } else if (bval == _BV(ISC50)) {
  110. *ival = NUT_IRQMODE_EDGE;
  111. } else if (bval == _BV(ISC51 | ISC50)) {
  112. *ival = NUT_IRQMODE_RISINGEDGE;
  113. } else {
  114. *ival = NUT_IRQMODE_LOWLEVEL;
  115. }
  116. break;
  117. case NUT_IRQCTL_SETMODE:
  118. if (*ival == NUT_IRQMODE_LOWLEVEL) {
  119. cbi(EICR, ISC50);
  120. cbi(EICR, ISC51);
  121. } else if (*ival == NUT_IRQMODE_EDGE) {
  122. sbi(EICR, ISC50);
  123. cbi(EICR, ISC51);
  124. } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
  125. cbi(EICR, ISC50);
  126. sbi(EICR, ISC51);
  127. } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
  128. sbi(EICR, ISC50);
  129. sbi(EICR, ISC51);
  130. } else {
  131. rc = -1;
  132. }
  133. break;
  134. case NUT_IRQCTL_GETPRIO:
  135. *ival = 5;
  136. break;
  137. #ifdef NUT_PERFMON
  138. case NUT_IRQCTL_GETCOUNT:
  139. *ival = (unsigned int) sig_INTERRUPT5.ir_count;
  140. sig_INTERRUPT5.ir_count = 0;
  141. break;
  142. #endif
  143. default:
  144. rc = -1;
  145. break;
  146. }
  147. /* Enable interrupt. */
  148. if (enabled) {
  149. sbi(EIMSK, INT5);
  150. }
  151. return rc;
  152. }
  153. /*! \fn INT5_vect(void)
  154. * \brief External interrupt 5 entry.
  155. */
  156. #ifdef __IMAGECRAFT__
  157. #pragma interrupt_handler INT5_vect:iv_INT5
  158. #endif
  159. NUTSIGNAL(INT5_vect, sig_INTERRUPT5)
  160. /*@}*/