ih_gpio0.c 6.4 KB

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  1. /*
  2. * Copyright (C) 2012 by Ole Reinhardt (ole.reinhardt@embedded-it.de)
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the copyright holders nor the names of
  16. * contributors may be used to endorse or promote products derived
  17. * from this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  26. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  27. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  29. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30. * SUCH DAMAGE.
  31. *
  32. * For additional information see http://www.ethernut.de/
  33. */
  34. #include <arch/avr32.h>
  35. #include <dev/irqreg.h>
  36. #include <avr32/io.h>
  37. #include <dev/gpio.h>
  38. #include <sys/atom.h>
  39. #include <arch/avr32/ihndlr.h>
  40. #ifndef NUT_IRQPRI_GPIO
  41. #define NUT_IRQPRI_GPIO 0
  42. #endif
  43. int GPIOpinNumber[] = {
  44. #if defined(AVR32_PIN_PA00)
  45. AVR32_PIN_PA00,
  46. #else
  47. -1,
  48. #endif
  49. #if defined(AVR32_PIN_PA01)
  50. AVR32_PIN_PA01,
  51. #else
  52. -1,
  53. #endif
  54. #if defined(AVR32_PIN_PA02)
  55. AVR32_PIN_PA02,
  56. #else
  57. -1,
  58. #endif
  59. AVR32_PIN_PA03,
  60. AVR32_PIN_PA04,
  61. AVR32_PIN_PA05,
  62. AVR32_PIN_PA06,
  63. AVR32_PIN_PA07,
  64. AVR32_PIN_PA08,
  65. AVR32_PIN_PA09,
  66. AVR32_PIN_PA10,
  67. AVR32_PIN_PA11,
  68. AVR32_PIN_PA12,
  69. AVR32_PIN_PA13,
  70. AVR32_PIN_PA14,
  71. AVR32_PIN_PA15,
  72. AVR32_PIN_PA16,
  73. AVR32_PIN_PA17,
  74. AVR32_PIN_PA18,
  75. AVR32_PIN_PA19,
  76. AVR32_PIN_PA20,
  77. AVR32_PIN_PA21,
  78. AVR32_PIN_PA22,
  79. };
  80. static int GpioIrqCtl(int cmd, void *param, int bit);
  81. GPIO_SIGNAL sig_GPIO = {
  82. NULL, /* ios_sig */
  83. NULL, /* ios_handler */
  84. GpioIrqCtl, /* ios_ctl */
  85. NULL, /* ios_vector */
  86. };
  87. /*!
  88. * \brief GPIO bank 0 interrupt entry.
  89. */
  90. SIGNAL(GPIO0IrqEntry)
  91. {
  92. IRQ_ENTRY();
  93. #ifdef NUT_PERFMON
  94. sig_GPIO.ir_count++;
  95. #endif
  96. GPIO_VECTOR *vct;
  97. volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[0];
  98. uint32_t ier = gpio_port->ier;
  99. uint32_t port_status = gpio_port->ifr & ier;
  100. vct = sig_GPIO.ios_vector;
  101. while (port_status) {
  102. if ((port_status & 1) != 0 && vct->iov_handler) {
  103. (vct->iov_handler) (vct->iov_arg);
  104. }
  105. port_status >>= 1;
  106. vct++;
  107. }
  108. // Clear interrupt
  109. // Workaround errata bug in UC3L, simply setting IRFC with interrupts enabled won't work.
  110. gpio_port->ierc = 0xffffffff;
  111. gpio_port->ifrc = 0xffffffff;
  112. gpio_port->pvr;
  113. gpio_port->iers = ier;
  114. IRQ_EXIT();
  115. }
  116. /*!
  117. * \brief Timer/Counter 0 interrupt control.
  118. *
  119. * \param cmd Control command.
  120. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  121. * - NUT_IRQCTL_STATUS Query interrupt status.
  122. * - NUT_IRQCTL_ENABLE Enable interrupt.
  123. * - NUT_IRQCTL_DISABLE Disable interrupt.
  124. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  125. * - NUT_IRQCTL_SETMODE Set interrupt mode (NUT_IRQMODE_LEVEL or NUT_IRQMODE_EDGE).
  126. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  127. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  128. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  129. * \param param Pointer to optional parameter.
  130. *
  131. * \return 0 on success, -1 otherwise.
  132. */
  133. static int GpioIrqCtl(int cmd, void *param, int bit)
  134. {
  135. int rc = 0;
  136. uint32_t *ival = (uint32_t *) param;
  137. volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[0];
  138. ureg_t ier = gpio_port->ier;
  139. int_fast8_t enabled = ier;
  140. /* Disable interrupt. */
  141. if (enabled) {
  142. gpio_port->ierc = 0xFFFFFFFF;
  143. }
  144. switch (cmd) {
  145. case NUT_IRQCTL_INIT:
  146. if ( GPIOpinNumber[bit] == -1 )
  147. rc = -1;
  148. else
  149. register_interrupt(GPIO0IrqEntry, AVR32_GPIO_IRQ_0 + (GPIOpinNumber[bit]/8), NUT_IRQPRI_GPIO);
  150. break;
  151. case NUT_IRQCTL_STATUS:
  152. if (ier & _BV(bit)) {
  153. *ival = 1;
  154. } else {
  155. *ival = 0;
  156. }
  157. break;
  158. case NUT_IRQCTL_ENABLE:
  159. ier |= _BV(bit);
  160. enabled = 1;
  161. break;
  162. case NUT_IRQCTL_DISABLE:
  163. ier &= ~_BV(bit);
  164. enabled = 0;
  165. break;
  166. case NUT_IRQCTL_GETMODE:
  167. if (((gpio_port->imr1 & _BV(bit)) == 0) && ((gpio_port->imr0 & _BV(bit)) == 1)) {
  168. *ival = NUT_IRQMODE_RISINGEDGE;
  169. } else if (((gpio_port->imr1 & _BV(bit)) == 1) && ((gpio_port->imr0 & _BV(bit)) == 0)) {
  170. *ival = NUT_IRQMODE_FALLINGEDGE;
  171. } else if (((gpio_port->imr1 & _BV(bit)) == 0) && ((gpio_port->imr0 & _BV(bit)) == 0)) {
  172. *ival = NUT_IRQMODE_BOTHEDGE;
  173. } else {
  174. *ival = NUT_IRQMODE_NONE;
  175. }
  176. break;
  177. case NUT_IRQCTL_SETMODE:
  178. switch (*ival) {
  179. case NUT_IRQMODE_RISINGEDGE:
  180. gpio_port->imr1 &= ~_BV(bit);
  181. gpio_port->imr0 |= _BV(bit);
  182. break;
  183. case NUT_IRQMODE_FALLINGEDGE:
  184. gpio_port->imr1 |= _BV(bit);
  185. gpio_port->imr0 &= ~_BV(bit);
  186. break;
  187. case NUT_IRQMODE_BOTHEDGE:
  188. gpio_port->imr1 &= ~_BV(bit);
  189. gpio_port->imr0 &= ~_BV(bit);
  190. break;
  191. default:
  192. rc = -1;
  193. }
  194. break;
  195. default:
  196. rc = -1;
  197. break;
  198. }
  199. /* Enable / disable interrupt and set mode */
  200. if (enabled) {
  201. gpio_port->iers = ier;
  202. }
  203. return rc;
  204. }