ih_stm32_exti.c 4.5 KB

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  1. /*
  2. * Copyright (C) 2010 by Ulrich Prinz (uprinz2@netscape.net)
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the copyright holders nor the names of
  16. * contributors may be used to endorse or promote products derived
  17. * from this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  26. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  27. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  29. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30. * SUCH DAMAGE.
  31. *
  32. * For additional information see http://www.ethernut.de/
  33. */
  34. /*!
  35. * \verbatim
  36. * $Id: ih_stm32_exti.c 5654 2014-04-07 14:02:06Z u_bonnes $
  37. * \endverbatim
  38. */
  39. #include <arch/cm3.h>
  40. #include <dev/irqreg.h>
  41. #include <dev/gpio.h>
  42. #include <arch/cm3/stm/stm32xxxx.h>
  43. /*!
  44. * \brief External interrupt 0 control.
  45. *
  46. * \param cmd Control command.
  47. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  48. * - NUT_IRQCTL_STATUS Query interrupt status.
  49. * - NUT_IRQCTL_ENABLE Enable interrupt.
  50. * - NUT_IRQCTL_DISABLE Disable interrupt.
  51. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  52. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  53. * \param param Pointer to optional parameter.
  54. *
  55. * \return 0 on success, -1 otherwise.
  56. */
  57. static int InterruptCtl(int cmd, void *param)
  58. {
  59. int rc = 0;
  60. unsigned int *ival = (unsigned int *)param;
  61. int enabled;
  62. #if (__CORTEX_M >= 0x03)
  63. enabled = (NVIC->ISER[((uint32_t)(THIS_IRQn) >> 5)] ==
  64. (1 << ((uint32_t)(THIS_IRQn) & 0x1F)));
  65. #else
  66. enabled = (NVIC->ISER[0] == (1 << ((uint32_t)(THIS_IRQn) & 0x1F)));
  67. #endif
  68. /* Disable interrupt. */
  69. if (enabled) {
  70. NVIC_DisableIRQ(THIS_IRQn);
  71. }
  72. switch(cmd) {
  73. case NUT_IRQCTL_INIT:
  74. /* Set the vector. */
  75. Cortex_RegisterInt(THIS_IRQn, THIS_ENTRY);
  76. /* Initialize with defined priority. */
  77. NVIC_SetPriority(THIS_IRQn, THIS_IRQPRI);
  78. /* Clear interrupt */
  79. NVIC_ClearPendingIRQ(THIS_IRQn);
  80. break;
  81. case NUT_IRQCTL_STATUS:
  82. if (enabled) {
  83. *ival |= 1;
  84. }
  85. else {
  86. *ival &= ~1;
  87. }
  88. break;
  89. case NUT_IRQCTL_ENABLE:
  90. enabled = 1;
  91. break;
  92. case NUT_IRQCTL_DISABLE:
  93. enabled = 0;
  94. break;
  95. /* This needs to be set at pin level configuration for the interrupt
  96. case NUT_IRQCTL_GETMODE:
  97. if ( EXTI->FTSR &= (1<<THIS_EXTI))
  98. *ival = NUT_IRQMODE_FALLINGEDGE;
  99. else if( EXTI->RTSR &= (1<<THIS_EXTI))
  100. *ival = NUT_IRQMODE_RISINGEDGE;
  101. break;
  102. case NUT_IRQCTL_SETMODE:
  103. if (*ival == NUT_IRQMODE_NONE) {
  104. EXTI->FTSR &= ~(1<<THIS_EXTI);
  105. EXTI->RTSR &= ~(1<<THIS_EXTI);
  106. }
  107. if (*ival == NUT_IRQMODE_FALLINGEDGE) {
  108. EXTI->FTSR |= (1<<THIS_EXTI);
  109. } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
  110. EXTI->RTSR |= (1<<THIS_EXTI);
  111. } else {
  112. rc = -1;
  113. }
  114. break;
  115. */
  116. case NUT_IRQCTL_GETPRIO:
  117. *ival = THIS_IRQPRI;
  118. break;
  119. #ifdef NUT_PERFMON
  120. case NUT_IRQCTL_GETCOUNT:
  121. *ival = (unsigned int)THIS_SIG.ir_count;
  122. THIS_SIG.ir_count = 0;
  123. break;
  124. #endif
  125. default:
  126. rc = -1;
  127. break;
  128. }
  129. /* Enable interrupt. */
  130. if (enabled) {
  131. NVIC_EnableIRQ(THIS_IRQn);
  132. }
  133. return rc;
  134. }