stm32_spi5.c 5.4 KB

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  1. /*
  2. * Copyright (C) 2010 by Ulrich Prinz (uprinz2@netscape.net)
  3. * Copyright (C) 2010 by Nikolaj Zamotaev. All rights reserved.
  4. * Copyright (C) 2014 by Uwe Bonnes.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the copyright holders nor the names of
  16. * contributors may be used to endorse or promote products derived
  17. * from this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  26. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  27. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  29. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30. * SUCH DAMAGE.
  31. *
  32. * For additional information see http://www.ethernut.de/
  33. *
  34. */
  35. /*
  36. * \verbatim
  37. * $Id: stm32_spi5.c 5716 2014-05-23 14:55:45Z u_bonnes $
  38. * \endverbatim
  39. */
  40. #include <arch/cm3.h>
  41. #include <sys/timer.h>
  42. #include <cfg/spi.h>
  43. #include <cfg/arch/gpio.h>
  44. #include <dev/spibus.h>
  45. #include <dev/gpio.h>
  46. #include <arch/cm3/stm/stm32_gpio.h>
  47. #include <arch/cm3/stm/stm32_spi.h>
  48. #include <dev/irqreg.h>
  49. #include <sys/event.h>
  50. #include <sys/nutdebug.h>
  51. #include <stdlib.h>
  52. #include <errno.h>
  53. /* Handle the PIN remap possibilities
  54. * F4
  55. * NSS: PF6/PH5
  56. * SCK: PF7/PH6
  57. * MISO: PF8/PH7
  58. * MOSI: PF9/PF11
  59. *
  60. *
  61. * For function pins, we use PF6/7/8/9 as default
  62. */
  63. #if !defined( SPIBUS5_NO_CS)
  64. #if !defined(SPIBUS5_CS0_PORT) & !defined(SPIBUS5_CS0_PIN)
  65. #define SPIBUS_CS0_PORT NUTGPIO_PORTF
  66. #define SPIBUS_CS0_PIN 6
  67. #elif !defined(SPIBUS2_CS0_PORT) || !defined(SPIBUS2_CS0_PIN)
  68. #warning "SPIBUS5 uncomplete chip select"
  69. #else
  70. #define SPIBUS_CS0_PORT SPIBUS5_CS0_PORT
  71. #define SPIBUS_CS0_PIN SPIBUS5_CS0_PIN
  72. #endif
  73. #if defined(SPIBUS5_CS1_PORT)
  74. #define SPIBUS_CS1_PORT SPIBUS5_CS1_PORT
  75. #endif
  76. #if defined(SPIBUS5_CS2_PORT)
  77. #define SPIBUS_CS2_PORT SPIBUS5_CS2_PORT
  78. #endif
  79. #if defined(SPIBUS5_CS3_PORT)
  80. #define SPIBUS_CS3_PORT SPIBUS5_CS3_PORT
  81. #endif
  82. #if defined(SPIBUS5_CS1_PIN)
  83. #define SPIBUS_CS1_PIN SPIBUS5_CS1_PIN
  84. #endif
  85. #if defined(SPIBUS5_CS2_PIN)
  86. #define SPIBUS_CS2_PIN SPIBUS5_CS2_PIN
  87. #endif
  88. #if defined(PIBUS5_CS2_PIN)
  89. #define SPIBUS_CS3_PIN SPIBUS5_CS3_PIN
  90. #endif
  91. #endif
  92. #if SPIBUS5_SCK_PIN == 6
  93. #define SPIBUS_SCK_PORT NUTGPIO_PORTH
  94. #define SPIBUS_SCK_PIN 6
  95. #else
  96. #define SPIBUS_SCK_PORT NUTGPIO_PORTF
  97. #define SPIBUS_SCK_PIN 7
  98. #endif
  99. #if SPIBUS5_MISO_PIN == 7
  100. #define SPIBUS_MISO_PORT NUTGPIO_PORTH
  101. #define SPIBUS_MISO_PIN 7
  102. #else
  103. #define SPIBUS_MISO_PORT NUTGPIO_PORTF
  104. #define SPIBUS_MISO_PIN 8
  105. #endif
  106. #if SPIBUS5_MOSI_PIN == 11
  107. #define SPIBUS_MOSI_PIN 11
  108. #else
  109. #define SPIBUS_MOSI_PIN 9
  110. #endif
  111. #define SPIBUS_MOSI_PORT NUTGPIO_PORTF
  112. #define SPI_GPIO_AF GPIO_AF_SPI5
  113. #define SPI_ENABLE_CLK_SET() CM3BBSET(RCC_BASE, RCC_TypeDef, APB2ENR, _BI32(RCC_APB2ENR_SPI5EN))
  114. #define SPI_ENABLE_CLK_GET() CM3BBGET(RCC_BASE, RCC_TypeDef, APB2ENR, _BI32(RCC_APB2ENR_SPI5EN))
  115. #define sig_SPI sig_SPI5
  116. #define SPI_BASE SPI5_BASE
  117. #if !defined(SPIBUS5_MODE)
  118. #define SPIBUS_MODE IRQ_MODE
  119. #else
  120. #define SPIBUS_MODE SPIBUS5_MODE
  121. #endif
  122. #if SPIBUS_MODE == DMA_MODE
  123. #if defined(SPIBUS1_DMA_TX_ALTERNATE_STREAM)
  124. #define SPI_DMA_TX_CHANNEL SPI5_TX_ALT_DMA
  125. #define sig_SPI_DMA_TX SPI5_TX_ALT_DMA_IRQ
  126. #else
  127. #define SPI_DMA_TX_CHANNEL SPI5_TX_DMA
  128. #define sig_SPI_DMA_TX SPI5_TX_DMA_IRQ
  129. #endif
  130. #if defined(SPIBUS1_DMA_RX_ALTERNATE_STREAM)
  131. #define SPI_DMA_RX_CHANNEL SPI5_RX_ALT_DMA
  132. #define sig_SPI_DMA_RX SPI5_RX_ALT_DMA_IRQ
  133. #else
  134. #define SPI_DMA_RX_CHANNEL SPI5_RX_DMA
  135. #define sig_SPI_DMA_RX SPI5_RX_DMA_IRQ
  136. #endif
  137. #endif
  138. NUTSPIBUS spiBus5Stm32 = {
  139. NULL, /*!< Bus mutex semaphore (bus_mutex). */
  140. NULL, /*!< Bus ready signal (bus_ready). */
  141. SPI5_BASE, /*!< Bus base address (bus_base). */
  142. NULL, /*!< Bus interrupt handler (bus_sig). */
  143. Stm32SpiBusNodeInit, /*!< Initialize the bus (bus_initnode). */
  144. Stm32SpiBusSelect, /*!< Select the specified device (bus_alloc). */
  145. Stm32SpiBusDeselect, /*!< Deselect the specified device (bus_release). */
  146. Stm32SpiBusTransfer,
  147. NutSpiBusWait,
  148. NutSpiBusSetMode, /*!< Set SPI mode of a specified device (bus_set_mode). */
  149. NutSpiBusSetRate, /*!< Set clock rate of a specified device (bus_set_rate). */
  150. NutSpiBusSetBits /*!< Set number of data bits of a specified device (bus_set_bits). */
  151. };
  152. #include "stm32_spi.c"