stm32f1_rtc.c 4.8 KB

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  1. /*
  2. * Copyright (C) 2010 by Ulrich Prinz (uprinz2@netscape.net)
  3. * Copyright (C) 2010 by Nikolaj Zamotaev. All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the distribution.
  14. * 3. Neither the name of the copyright holders nor the names of
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  21. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  22. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  23. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  24. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  25. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  26. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  27. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  28. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29. * SUCH DAMAGE.
  30. *
  31. * For additional information see http://www.ethernut.de/
  32. *
  33. */
  34. /*
  35. * \verbatim
  36. * $Id: stm32f1_rtc.c 5381 2013-10-07 11:01:12Z u_bonnes $
  37. * \endverbatim
  38. */
  39. #include <cfg/os.h>
  40. #include <cfg/clock.h>
  41. #include <cfg/arch.h>
  42. #include <sys/event.h>
  43. #include <sys/timer.h>
  44. #include <dev/rtc.h>
  45. #include <cfg/arch/gpio.h>
  46. #include <arch/cm3/stm/vendor/stm32f10x.h>
  47. #include <stdlib.h>
  48. #include <string.h>
  49. #include <time.h>
  50. static void Stm32RtcRtoffPoll(void)
  51. {
  52. while((RTC->CRL & RTC_CRL_RTOFF)==0);
  53. return;
  54. };
  55. /*!
  56. * \brief Get date and time from an DS1307 hardware clock.
  57. *
  58. * \param tm Points to a structure that receives the date and time
  59. * information.
  60. *
  61. * \return 0 on success or -1 in case of an error.
  62. */
  63. int Stm32RtcGetClock(NUTRTC *rtc, struct _tm *tm)
  64. {
  65. int rc=-1;
  66. time_t time;
  67. RTC->CRL&= ~(RTC_CRL_RSF);
  68. while(!(RTC->CRL & RTC_CRL_RSF));
  69. time=((RTC->CNTL|(RTC->CNTH<<16)));
  70. localtime_r(&time,tm);
  71. rc=0;
  72. return rc;
  73. }
  74. /*!
  75. * \brief Set the DS1307 hardware clock.
  76. *
  77. * \param tm Points to a structure which contains the date and time
  78. * information.
  79. *
  80. * \return 0 on success or -1 in case of an error.
  81. */
  82. int Stm32RtcSetClock(NUTRTC *rtc, const struct _tm *tm)
  83. {
  84. time_t time;
  85. Stm32RtcRtoffPoll();
  86. RTC->CRL|= RTC_CRL_CNF;
  87. time=mktime((struct _tm *)tm);
  88. RTC->CNTL =time& 0xffffUL;
  89. RTC->CNTH =(time >> 16) &0xffffUL;
  90. RTC->CRL&= ~(RTC_CRL_CNF);
  91. Stm32RtcRtoffPoll();
  92. return 0;
  93. }
  94. /*!
  95. * \brief Initialize the RTC in stm32f10x controller
  96. *
  97. * \return 0 on success or -1 in case of an error.
  98. *
  99. */
  100. int Stm32RtcInit(NUTRTC *rtc)
  101. {
  102. int rc=-1;
  103. uint32_t temp;
  104. RCC->APB1ENR |= RCC_APB1ENR_BKPEN|RCC_APB1ENR_PWREN;
  105. PWR->CR |= PWR_CR_DBP;
  106. RCC->BDCR|= (1<<16);//Backup domain reset;
  107. RCC->BDCR&= ~(1<<16);//Backup domain reset;
  108. PWR->CR|= PWR_CR_DBP;
  109. temp=RCC->BDCR;
  110. temp&= ~(RCC_BDCR_RTCSEL);
  111. /*Fixme: Don't assume fixed HSE frequency here*/
  112. temp |= RCC_BDCR_RTCSEL;//HSE/128
  113. temp |= RCC_BDCR_RTCEN;
  114. RCC->BDCR=temp;
  115. RTC->CRL&= ~(RTC_CRL_RSF);
  116. while(!(RTC->CRL & RTC_CRL_RSF));
  117. Stm32RtcRtoffPoll();
  118. RTC->CRL|= RTC_CRL_CNF;
  119. RTC->PRLH = 0;
  120. RTC->PRLL = (8000000ul/128)-1;//äÌÑ ÄÅÌÉÔÅÌÑ ÎÁ 128 ÏÔ Ë×ÁÒÃÁ 8íçÃ
  121. //õÓÔÁÎÁ×ÌÉ×ÁÅÍ ×ÍÅÎÑÅÍÏÅ ×ÒÅÍÑ
  122. RTC->CNTL= 1;
  123. RTC->CNTH= 0;//1 january 1970
  124. RTC->CRL&= ~(RTC_CRL_CNF);
  125. Stm32RtcRtoffPoll();
  126. rc=0;
  127. return rc;
  128. }
  129. NUTRTC rtcStm32 = {
  130. /*.dcb = */ NULL, /*!< Driver control block */
  131. /*.rtc_init = */ Stm32RtcInit, /*!< Hardware initializatiuon, rtc_init */
  132. /*.rtc_gettime = */ Stm32RtcGetClock, /*!< Read date and time, rtc_gettime */
  133. /*.rtc_settime = */ Stm32RtcSetClock, /*!< Set date and time, rtc_settime */
  134. /*.rtc_getalarm = */ NULL, /*!< Read alarm date and time, rtc_getalarm */
  135. /*.rtc_setalarm = */ NULL, /*!< Set alarm date and time, rtc_setalarm */
  136. /*.rtc_getstatus = */ NULL, /*!< Read status flags, rtc_getstatus */
  137. /*.rtc_clrstatus = */ NULL, /*!< Clear status flags, rtc_clrstatus */
  138. /*.alarm = */ NULL, /*!< Handle for alarm event queue, not supported right now */
  139. };