stm32pll.nut 5.1 KB

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  1. --
  2. -- STM32 PLL Configuration
  3. --
  4. nutarch_cm3_stm32_pll =
  5. {
  6. {
  7. name = "nutarch_cm3_stm32L1_pll",
  8. brief = "STM32L1 PLL Setup",
  9. options =
  10. {
  11. {
  12. macro = "SYSCLK_SOURCE",
  13. brief = "SYSCLK Source",
  14. description = "Select where SYSCLK should get its clock from.\n\n"..
  15. "SYSCLK_HSI is the internal 8MHz clock.\n"..
  16. "SYSCLK_PLL is the internal PLL output. Select the source for the PLL in the next option.\n"..
  17. "SYSCLK_HSE is the external oscillator or crystal input.\n",
  18. type = "enumerated",
  19. choices = { "SYSCLK_HSI", "SYSCLK_PLL", "SYSCLK_HSE" },
  20. file = "include/cfg/clock.h"
  21. },
  22. {
  23. macro = "PLLCLK_SOURCE",
  24. brief = "PLL Clock Source",
  25. description = "Select where the PLL should get its clock from.\n\n"..
  26. "SYSCLK_HSI is the internal 8MHz clock. PLL is fed with SYSCLK_HSI/2.\n"..
  27. "SYSCLK_HSE is the external oscillator or crystal input.\n",
  28. type = "enumerated",
  29. choices = { "PLLCLK_HSI", "PLLCLK_HSE" },
  30. file = "include/cfg/clock.h"
  31. },
  32. {
  33. macro = "HSE_BYPASS",
  34. brief = "HSE from external source",
  35. description = "Use the clock signal applied to OSC_IN.",
  36. flavor = "booldata",
  37. file = "include/cfg/clock.h"
  38. },
  39. {
  40. macro = "HSE_VALUE",
  41. brief = "External Oszillator Frequency",
  42. description = "Value of the external oscillator in Herz.\n"..
  43. "Allowed values:\n"..
  44. " STM32F0xx : 1.. 32 Mhz\n"..
  45. " STM32F100 : 4.. 24 Mhz\n"..
  46. " STM32F101 : 4.. 16 Mhz\n"..
  47. " STM32F102/3: 1.. 25 Mhz\n"..
  48. " STM32F105/7: 3.. 25 Mhz\n"..
  49. " STM32F20X : 1.. 26 Mhz\n"..
  50. " STM32F3XX : 1.. 32 Mhz\n"..
  51. " STM32F4XX : 1.. 50 Mhz\n"..
  52. "Typical Values is 8MHz. On F105/7 DFU bootloader works\n"..
  53. "better with 25 MHz\n",
  54. flavor = "integer",
  55. type = "long",
  56. default = "8000000",
  57. file = "include/cfg/clock.h"
  58. },
  59. {
  60. macro = "SYSCLK_FREQ",
  61. brief = "CM3 System Clock",
  62. description = "System clock (SYSCLK) target frequency.\n"..
  63. "Allowed values:\n"..
  64. "Allowed values:\n"..
  65. " STM32F0XX : 48 Mhz\n"..
  66. " STM32F100 : 24 Mhz\n"..
  67. " STM32F101 : 36 Mhz\n"..
  68. " STM32F102/3 : 48 Mhz\n"..
  69. " STM32F105/7 : 72 Mhz\n"..
  70. " STM32F20X : 120 Mhz\n"..
  71. " STM32F3XX : 72 Mhz\n"..
  72. " STM32F401 : 72 Mhz\n"..
  73. " STM32F40_1X : 168 Mhz\n"..
  74. " STM32F42_3X : 184 Mhz\n",
  75. flavor = "integer",
  76. type = "long",
  77. file = "include/cfg/clock.h"
  78. },
  79. {
  80. macro = "PLLCLK_MULT",
  81. brief = "PLL Clock Multiplier",
  82. description = "In many cases HSE_VALUE and SYSCLK_FREQ is enough for the code\n"..
  83. "to calculate PLLCLK_MULT and PLLCLK_DIV. If code is unable,\n"..
  84. "enter non-zero integer PLL Clock Multiplier value here\n",
  85. flavor = "integer",
  86. default = "0",
  87. file = "include/cfg/clock.h"
  88. },
  89. {
  90. macro = "PLLCLK_DIV",
  91. brief = "PLL Clock Divider",
  92. description = "In many cases HSE_VALUE and SYSCLK_FREQ is enough for the code\n"..
  93. "to calculate PLLCLK_MULT and PLLCLK_DIV. If code is unable,\n"..
  94. "enter non-zero integer PLL Clock Divider value here\n",
  95. flavor = "integer",
  96. default = "0",
  97. file = "include/cfg/clock.h"
  98. },
  99. },
  100. },
  101. }