spibus_npl.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2008-2009 by egnite GmbH
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the copyright holders nor the names of
  16. * contributors may be used to endorse or promote products derived
  17. * from this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  26. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  27. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  29. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30. * SUCH DAMAGE.
  31. *
  32. * For additional information see http://www.ethernut.de/
  33. */
  34. /*!
  35. * \file arch/arm/dev/spibus_npl.c
  36. * \brief General SPI bus controller routines for Nut Programmable Logic.
  37. *
  38. * \verbatim
  39. * $Id$
  40. * \endverbatim
  41. */
  42. #include <cfg/spi.h>
  43. #include <sys/timer.h>
  44. #include <sys/nutdebug.h>
  45. #include <stdlib.h>
  46. #include <memdebug.h>
  47. #include <errno.h>
  48. #include <dev/cy2239x.h>
  49. #include <dev/npl.h>
  50. #include <dev/spibus_npl.h>
  51. #ifndef NPL_MMC_CLOCK
  52. #define NPL_MMC_CLOCK 12500000
  53. #endif
  54. /*!
  55. * \brief Update SPI shadow registers.
  56. *
  57. * \param node Specifies the SPI bus node.
  58. *
  59. * \return Always 0.
  60. */
  61. static int NplSpiSetup(NUTSPINODE * node)
  62. {
  63. #if defined(NUT_PLL_NPLCLK1)
  64. uint32_t clk;
  65. uint32_t clkdiv;
  66. NUTASSERT(node != NULL);
  67. /* Query the PLL number routed to Clock B. */
  68. clk = Cy2239xGetPll(NUT_PLL_NPLCLK1);
  69. /* Get the frequency of this PLL. */
  70. clk = Cy2239xPllGetFreq((int)clk, 7);
  71. /* Calculate the required divider value. */
  72. clkdiv = (clk + NPL_MMC_CLOCK - 10) / NPL_MMC_CLOCK;
  73. /*
  74. * Not sure about the Cy-routines. The DIVSEL bit specifies which
  75. * divider is used, which is indirectly connected to S2, which is
  76. * high by default. For now set both dividers.
  77. */
  78. if (Cy2239xSetDivider(NUT_PLL_NPLCLK1, 1, (int)clkdiv)) {
  79. return -1;
  80. }
  81. if (Cy2239xSetDivider(NUT_PLL_NPLCLK1, 0, (int)clkdiv)) {
  82. return -1;
  83. }
  84. /* Update interface parameters. */
  85. node->node_rate = clk / clkdiv;
  86. node->node_mode &= ~SPI_MODE_UPDATE;
  87. #endif
  88. return 0;
  89. }
  90. /*!
  91. * \brief Set the specified chip select to a given level.
  92. *
  93. * \param cs Chip select number, 0 for MMC, 1 of DataFlash
  94. * \param hi Chip select line is activated if 0, deactivated if 1.
  95. *
  96. * \return 0 on success or -1 if the specified chip select number is not
  97. * supported.
  98. */
  99. static int NplSpiChipSelect(uint_fast8_t cs, uint_fast8_t hi)
  100. {
  101. int rc = 0;
  102. switch (cs) {
  103. case 0:
  104. if (hi) {
  105. outb(NPL_XER, inb(NPL_XER) | NPL_MMCS);
  106. } else {
  107. outb(NPL_XER, inb(NPL_XER) & ~NPL_MMCS);
  108. }
  109. break;
  110. case 1:
  111. if (hi) {
  112. outb(NPL_XER, inb(NPL_XER) | NPL_NPCS0);
  113. } else {
  114. outb(NPL_XER, inb(NPL_XER) & ~NPL_NPCS0);
  115. }
  116. break;
  117. default:
  118. errno = EIO;
  119. rc = -1;
  120. break;
  121. }
  122. return rc;
  123. }
  124. /*! \brief Select a device on the first SPI bus.
  125. *
  126. * Locks and activates the bus for the specified node.
  127. *
  128. * \param node Specifies the SPI bus node.
  129. * \param tmo Timeout in milliseconds. To disable timeout, set this
  130. * parameter to NUT_WAIT_INFINITE.
  131. *
  132. * \return 0 on success. In case of an error, -1 is returned and the bus
  133. * is not locked.
  134. */
  135. int NplSpiBusSelect(NUTSPINODE * node, uint32_t tmo)
  136. {
  137. int rc;
  138. /* Sanity check. */
  139. NUTASSERT(node != NULL);
  140. NUTASSERT(node->node_bus != NULL);
  141. /* Allocate the bus. */
  142. rc = NutEventWait(&node->node_bus->bus_mutex, tmo);
  143. if (rc) {
  144. errno = EIO;
  145. } else {
  146. /* If the mode update bit is set, then update our shadow registers. */
  147. if (node->node_mode & SPI_MODE_UPDATE) {
  148. NplSpiSetup(node);
  149. }
  150. /* Finally activate the node's chip select. */
  151. rc = NplSpiChipSelect(node->node_cs, 0);
  152. if (rc) {
  153. /* Release the bus in case of an error. */
  154. NutEventPost(&node->node_bus->bus_mutex);
  155. }
  156. }
  157. return rc;
  158. }
  159. /*! \brief Deselect a device on the first SPI bus.
  160. *
  161. * Deactivates the chip select and unlocks the bus.
  162. *
  163. * \param node Specifies the SPI bus node.
  164. *
  165. * \return Always 0.
  166. */
  167. int NplSpiBusDeselect(NUTSPINODE * node)
  168. {
  169. /* Sanity check. */
  170. NUTASSERT(node != NULL);
  171. NUTASSERT(node->node_bus != NULL);
  172. /* Deactivate the node's chip select. */
  173. NplSpiChipSelect(node->node_cs, 1);
  174. /* Release the bus. */
  175. NutEventPost(&node->node_bus->bus_mutex);
  176. return 0;
  177. }
  178. /*!
  179. * \brief Initialize an SPI bus node.
  180. *
  181. * This routine is called for each SPI node, which is registered via
  182. * NutRegisterSpiDevice().
  183. *
  184. * \param node Specifies the SPI bus node.
  185. *
  186. * \return 0 on success or -1 if there is no valid chip select.
  187. */
  188. int NplSpiBusNodeInit(NUTSPINODE * node)
  189. {
  190. int rc;
  191. /* Sanity check. */
  192. NUTASSERT(node != NULL);
  193. /* Try to deactivate the node's chip select. */
  194. rc = NplSpiChipSelect(node->node_cs, 1);
  195. if (rc == 0) {
  196. NplSpiSetup(node);
  197. }
  198. return rc;
  199. }
  200. /*!
  201. * \brief Transfer data on the SPI bus in polling mode.
  202. *
  203. * A device must have been selected by calling NplSpiSelect().
  204. *
  205. * \param node Specifies the SPI bus node.
  206. * \param txbuf Pointer to the transmit buffer. If NULL, undetermined
  207. * byte values are transmitted.
  208. * \param rxbuf Pointer to the receive buffer. If NULL, then incoming
  209. * data is discarded.
  210. * \param xlen Number of bytes to transfer.
  211. *
  212. * \return Always 0.
  213. */
  214. int NplSpiBusPollTransfer(NUTSPINODE * node, const void *txbuf, void *rxbuf, int xlen)
  215. {
  216. uint8_t rxc;
  217. uint8_t txc = 0xFF;
  218. uint8_t *txp = (uint8_t *) txbuf;
  219. uint8_t *rxp = (uint8_t *) rxbuf;
  220. /* Sanity check. */
  221. NUTASSERT(node != NULL);
  222. while (xlen--) {
  223. if (txp) {
  224. txc = *txp++;
  225. }
  226. /* Transmission starts by writing the transmit data. */
  227. outb(NPL_MMCDR, txc);
  228. /* Wait for receiver data register full. */
  229. while ((inb(NPL_SLR) & NPL_MMCREADY) == 0);
  230. /* Read incoming data. */
  231. rxc = inb(NPL_MMCDR);
  232. if (rxp) {
  233. *rxp++ = rxc;
  234. }
  235. }
  236. return 0;
  237. }
  238. /*!
  239. * \brief SPI bus driver implementation structure.
  240. */
  241. NUTSPIBUS spiBusNpl = {
  242. NULL, /*!< Bus mutex semaphore (bus_mutex). */
  243. NULL, /*!< Bus ready signal (bus_ready). */
  244. 0, /*!< Bus base address (bus_base). */
  245. NULL, /*!< Bus interrupt handler (bus_sig). */
  246. NplSpiBusNodeInit, /*!< Initialize the bus (bus_initnode). */
  247. NplSpiBusSelect, /*!< Select the specified device (bus_alloc). */
  248. NplSpiBusDeselect, /*!< Deselect the specified device (bus_release). */
  249. NplSpiBusPollTransfer, /*!< Transfer data to and from a specified node (bus_transfer). */
  250. NutSpiBusWait, /*!< Wait for bus transfer ready (bus_wait). */
  251. NutSpiBusSetMode, /*!< Set SPI mode of a specified device (bus_set_mode). */
  252. NutSpiBusSetRate, /*!< Set clock rate of a specified device (bus_set_rate). */
  253. NutSpiBusSetBits /*!< Set number of data bits of a specified device (bus_set_bits). */
  254. };