صفحهٔ اصلی گشت‌و‌گذار راهنما
ثبت نام ورود
Avans-TI
/
2.3-InternetRadio
2
0
انشعاب 0
پرونده‌ها مشکلات 0 درخواست واکشی 0 ویکی
درخت: b12fac4b8e
شاخه‌ها تگ‌ها
2.3-InternetRad...
/
nutos
/
nut
/
include
/
arch
/
arm
/
atmel
/
at91_lcdc.h

at91_lcdc.h 11 KB
تاريخچه خام

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137 
  1. #ifndef _ARCH_ARM_AT91_LCDC_H_
    2. 

  2. #define _ARCH_ARM_AT91_LCDC_H_
    3. 

  3. 

  4. /*
    5. 

  5.  * Copyright (C) 2010 by egnite GmbH
    6. 

  6.  *
    7. 

  7.  * All rights reserved.
    8. 

  8.  *
    9. 

  9.  * Redistribution and use in source and binary forms, with or without
    10. 

  10.  * modification, are permitted provided that the following conditions
    11. 

  11.  * are met:
    12. 

  12.  *
    13. 

  13.  * 1. Redistributions of source code must retain the above copyright
    14. 

  14.  *    notice, this list of conditions and the following disclaimer.
    15. 

  15.  * 2. Redistributions in binary form must reproduce the above copyright
    16. 

  16.  *    notice, this list of conditions and the following disclaimer in the
    17. 

  17.  *    documentation and/or other materials provided with the distribution.
    18. 

  18.  * 3. Neither the name of the copyright holders nor the names of
    19. 

  19.  *    contributors may be used to endorse or promote products derived
    20. 

  20.  *    from this software without specific prior written permission.
    21. 

  21.  *
    22. 

  22.  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    23. 

  23.  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    24. 

  24.  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
    25. 

  25.  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
    26. 

  26.  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    27. 

  27.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    28. 

  28.  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    29. 

  29.  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
    30. 

  30.  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
    31. 

  31.  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
    32. 

  32.  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
    33. 

  33.  * SUCH DAMAGE.
    34. 

  34.  *
    35. 

  35.  * For additional information see http://www.ethernut.de/
    36. 

  36.  */
    37. 

  37. 

  38. /*!
    39. 

  39.  * \addtogroup xgNutArchArmAt91Lcd
    40. 

  40.  */
    41. 

  41. /*@{*/
    42. 

  42. 

  43. #ifdef LCDC_BASE
    44. 

  44. 

  45. /*! \name LCD Controller Register */
    46. 

  46. /*@{*/
    47. 

  47. 

  48. #define LCDC_DMABADDR1_OFF             0x00000000                       /*!< \brief DMA Base Address Register 1. */
    49. 

  49. #define LCDC_DMABADDR2_OFF             0x00000004                       /*!< \brief DMA Base Address Register 2. */
    50. 

  50. #define LCDC_DMAFRMPT1_OFF             0x00000008                       /*!< \brief DMA Frame Pointer Register 1. */
    51. 

  51. #define LCDC_DMAFRMPT2_OFF             0x0000000C                       /*!< \brief DMA Frame Pointer Register 2. */
    52. 

  52. #define LCDC_DMAFRMADD1_OFF            0x00000010                       /*!< \brief DMA Frame Address Register 1. */
    53. 

  53. #define LCDC_DMAFRMADD2_OFF            0x00000014                       /*!< \brief DMA Frame Address Register 2. */
    54. 

  54. #define LCDC_DMAFRMCFG_OFF             0x00000018                       /*!< \brief DMA Frame Configuration Register. */
    55. 

  55. #define LCDC_DMACON_OFF                0x0000001C                       /*!< \brief DMA Control Register. */
    56. 

  56. #define LCDC_DMA2DCFG_OFF              0x00000020                       /*!< \brief DMA Control Register. */
    57. 

  57. #define LCDC_LCDCON1_OFF               0x00000800                       /*!< \brief LCD Control Register 1. */
    58. 

  58. #define LCDC_LCDCON2_OFF               0x00000804                       /*!< \brief LCD Control Register 2. */
    59. 

  59. #define LCDC_LCDTIM1_OFF               0x00000808                       /*!< \brief LCD Timing Register 1. */
    60. 

  60. #define LCDC_LCDTIM2_OFF               0x0000080C                       /*!< \brief LCD Timing Register 2. */
    61. 

  61. #define LCDC_LCDFRMCFG_OFF             0x00000810                       /*!< \brief LCD Frame Configuration Register. */
    62. 

  62. #define LCDC_LCDFIFO_OFF               0x00000814                       /*!< \brief LCD FIFO Register. */
    63. 

  63. #define LCDC_LCDMVAL_OFF               0x00000818                       /*!< \brief LCDMOD Toggle Rate Value Register. */
    64. 

  64. #define LCDC_DP1_2_OFF                 0x0000081C                       /*!< \brief Dithering Pattern DP1_2. */
    65. 

  65. #define LCDC_DP4_7_OFF                 0x00000820                       /*!< \brief Dithering Pattern DP4_7. */
    66. 

  66. #define LCDC_DP3_5_OFF                 0x00000824                       /*!< \brief Dithering Pattern DP3_5. */
    67. 

  67. #define LCDC_DP2_3_OFF                 0x00000828                       /*!< \brief Dithering Pattern DP2_3. */
    68. 

  68. #define LCDC_DP5_7_OFF                 0x0000082C                       /*!< \brief Dithering Pattern DP5_7. */
    69. 

  69. #define LCDC_DP3_4_OFF                 0x00000830                       /*!< \brief Dithering Pattern DP3_4. */
    70. 

  70. #define LCDC_DP4_5_OFF                 0x00000834                       /*!< \brief Dithering Pattern DP4_5. */
    71. 

  71. #define LCDC_DP6_7_OFF                 0x00000838                       /*!< \brief Dithering Pattern DP6_7. */
    72. 

  72. #define LCDC_PWRCON_OFF                0x0000083C                       /*!< \brief Power Control Register. */
    73. 

  73. #define LCDC_CONTRAST_CTR_OFF          0x00000840                       /*!< \brief Contrast Control Register. */
    74. 

  74. #define LCDC_CONTRAST_VAL_OFF          0x00000844                       /*!< \brief Contrast Value Register. */
    75. 

  75. #define LCDC_LCD_IER_OFF               0x00000848                       /*!< \brief LCD Interrupt Enable Register. */
    76. 

  76. #define LCDC_LCD_IDR_OFF               0x0000084C                       /*!< \brief LCD Interrupt Disable Register. */
    77. 

  77. #define LCDC_LCD_IMR_OFF               0x00000850                       /*!< \brief LCD Interrupt Mask Register. */
    78. 

  78. #define LCDC_LCD_ISR_OFF               0x00000854                       /*!< \brief LCD Interrupt Status Register. */
    79. 

  79. #define LCDC_LCD_ICR_OFF               0x00000858                       /*!< \brief LCD Interrupt Clear Register. */
    80. 

  80. #define LCDC_LCD_ITR_OFF               0x00000860                       /*!< \brief LCD Interrupt Test Register. */
    81. 

  81. #define LCDC_LCD_IRR_OFF               0x00000864                       /*!< \brief LCD Interrupt Raw Status Register. */
    82. 

  82. #define LCDC_LCD_WPCR_OFF              0x000008E4                       /*!< \brief Write Protection Control Register. */
    83. 

  83. #define LCDC_LCD_WPSR_OFF              0x000008E8                       /*!< \brief Write Protection Status Register. */
    84. 

  84. #define LCDC_LUT_ENTRY_0_OFF           0x00000C00                       /*!< \brief Palette entry 0. */
    85. 

  85. #define LCDC_LUT_ENTRY_1_OFF           0x00000C04                       /*!< \brief Palette entry 1. */
    86. 

  86. #define LCDC_LUT_ENTRY_2_OFF           0x00000C08                       /*!< \brief Palette entry 2. */
    87. 

  87. /* ... */
    88. 

  88. #define LCDC_LUT_ENTRY_255_OFF         0x00000FFC                       /*!< \brief Palette entry 255. */
    89. 

  89. 

  90. #define LCDC_DMABADDR1                          (LCDC_BASE + LCDC_DMABADDR1_OFF)            /*!< \brief DMA Base Address Register 1. */
    91. 

  91. #define LCDC_DMABADDR2                          (LCDC_BASE + LCDC_DMABADDR2_OFF)      /*!< \brief DMA Base Address Register 2. */
    92. 

  92. #define LCDC_DMAFRMPT1                          (LCDC_BASE + LCDC_DMAFRMPT1_OFF)      /*!< \brief DMA Frame Pointer Register 1. */
    93. 

  93. #define LCDC_DMAFRMPT2                          (LCDC_BASE + LCDC_DMAFRMPT2_OFF)      /*!< \brief DMA Frame Pointer Register 2. */
    94. 

  94. #define LCDC_DMAFRMADD1                         (LCDC_BASE + LCDC_DMAFRMADD1_OFF)     /*!< \brief DMA Frame Address Register 1. */
    95. 

  95. #define LCDC_DMAFRMADD2                         (LCDC_BASE + LCDC_DMAFRMADD2_OFF)     /*!< \brief DMA Frame Address Register 2. */
    96. 

  96. #define LCDC_DMAFRMCFG                          (LCDC_BASE + LCDC_DMAFRMCFG_OFF)      /*!< \brief DMA Frame Configuration Register. */
    97. 

  97. #define LCDC_DMACON                               (LCDC_BASE + LCDC_DMACON_OFF)         /*!< \brief DMA Control Register. */
    98. 

  98. #define LCDC_DMA2DCFG                               (LCDC_BASE + LCDC_DMA2DCFG_OFF)       /*!< \brief DMA Control Register. */
    99. 

  99. #define LCDC_LCDCON1                                (LCDC_BASE + LCDC_LCDCON1_OFF)        /*!< \brief LCD Control Register 1. */
    100. 

  100. #define LCDC_LCDCON2                                (LCDC_BASE + LCDC_LCDCON2_OFF)        /*!< \brief LCD Control Register 2. */
    101. 

  101. #define LCDC_LCDTIM1                                (LCDC_BASE + LCDC_LCDTIM1_OFF)        /*!< \brief LCD Timing Register 1. */
    102. 

  102. #define LCDC_LCDTIM2                                (LCDC_BASE + LCDC_LCDTIM2_OFF)        /*!< \brief LCD Timing Register 2. */
    103. 

  103. #define LCDC_LCDFRMCFG                          (LCDC_BASE + LCDC_LCDFRMCFG_OFF)       /*!< \brief LCD Frame Configuration Register. */
    104. 

  104. #define LCDC_LCDFIFO                                (LCDC_BASE + LCDC_LCDFIFO_OFF)        /*!< \brief LCD FIFO Register. */
    105. 

  105. #define LCDC_LCDMVAL                          (LCDC_BASE + LCDC_LCDMVAL_OFF)        /*!< \brief LCDMOD Toggle Rate Value Register. */
    106. 

  106. #define LCDC_DP1_2                              (LCDC_BASE + LCDC_DP1_2_OFF)                /*!< \brief Dithering Pattern DP1_2. */
    107. 

  107. #define LCDC_DP4_7                                (LCDC_BASE + LCDC_DP4_7_OFF)          /*!< \brief Dithering Pattern DP4_7. */
    108. 

  108. #define LCDC_DP3_5                                (LCDC_BASE + LCDC_DP3_5_OFF)          /*!< \brief Dithering Pattern DP3_5. */
    109. 

  109. #define LCDC_DP2_3                                (LCDC_BASE + LCDC_DP2_3_OFF)          /*!< \brief Dithering Pattern DP2_3. */
    110. 

  110. #define LCDC_DP5_7                                (LCDC_BASE + LCDC_DP5_7_OFF)          /*!< \brief Dithering Pattern DP5_7. */
    111. 

  111. #define LCDC_DP3_4                                (LCDC_BASE + LCDC_DP3_4_OFF)          /*!< \brief Dithering Pattern DP3_4. */
    112. 

  112. #define LCDC_DP4_5                                (LCDC_BASE + LCDC_DP4_5_OFF)          /*!< \brief Dithering Pattern DP4_5. */
    113. 

  113. #define LCDC_DP6_7                                (LCDC_BASE + LCDC_DP6_7_OFF)          /*!< \brief Dithering Pattern DP6_7. */
    114. 

  114. #define LCDC_PWRCON                               (LCDC_BASE + LCDC_PWRCON_OFF)         /*!< \brief Power Control Register. */
    115. 

  115. #define LCDC_CONTRAST_CTR                       (LCDC_BASE + LCDC_CONTRAST_CTR_OFF)   /*!< \brief Contrast Control Register. */
    116. 

  116. #define LCDC_CONTRAST_VAL                       (LCDC_BASE + LCDC_CONTRAST_VAL_OFF)   /*!< \brief Contrast Value Register. */
    117. 

  117. #define LCDC_LCD_IER                                (LCDC_BASE + LCDC_LCD_IER_OFF)        /*!< \brief LCD Interrupt Enable Register. */
    118. 

  118. #define LCDC_LCD_IDR                                (LCDC_BASE + LCDC_LCD_IDR_OFF)        /*!< \brief LCD Interrupt Disable Register. */
    119. 

  119. #define LCDC_LCD_IMR                                (LCDC_BASE + LCDC_LCD_IMR_OFF)        /*!< \brief LCD Interrupt Mask Register. */
    120. 

  120. #define LCDC_LCD_ISR                                (LCDC_BASE + LCDC_LCD_ISR_OFF)        /*!< \brief LCD Interrupt Status Register. */
    121. 

  121. #define LCDC_LCD_ICR                                (LCDC_BASE + LCDC_LCD_ICR_OFF)        /*!< \brief LCD Interrupt Clear Register. */
    122. 

  122. #define LCDC_LCD_ITR                                (LCDC_BASE + LCDC_LCD_ITR_OFF)        /*!< \brief LCD Interrupt Test Register. */
    123. 

  123. #define LCDC_LCD_IRR                                (LCDC_BASE + LCDC_LCD_IRR_OFF)        /*!< \brief LCD Interrupt Raw Status Register. */
    124. 

  124. #define LCDC_LCD_WPCR                               (LCDC_BASE + LCDC_LCD_WPCR_OFF)       /*!< \brief Write Protection Control Register. */
    125. 

  125. #define LCDC_LCD_WPSR                               (LCDC_BASE + LCDC_LCD_WPSR_OFF)       /*!< \brief Write Protection Status Register. */
    126. 

  126. #define LCDC_LUT_ENTRY_0                        (LCDC_BASE + LCDC_LUT_ENTRY_0_OFF)    /*!< \brief Palette entry 0. */
    127. 

  127. #define LCDC_LUT_ENTRY_1                        (LCDC_BASE + LCDC_LUT_ENTRY_1_OFF)    /*!< \brief Palette entry 1. */
    128. 

  128. #define LCDC_LUT_ENTRY_2                        (LCDC_BASE + LCDC_LUT_ENTRY_2_OFF)    /*!< \brief Palette entry 2. */
    129. 

  129. /* ... */
    130. 

  130. #define LCDC_LUT_ENTRY_255                  (LCDC_BASE + LCDC_LUT_ENTRY_255_OFF)  /*!< \brief Palette entry 255. */
    131. 

  131. /*@}*/
    132. 

  132. 

  133. /*@} xgNutArchArmAt91Lcd */
    134. 

  134. 

  135. #endif /* LCDC_BASE */
    136. 

  136. 

  137. #endif /* _ARCH_ARM_AT91_LCDC_H_ */
    138.