at91_udp.h 8.5 KB

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  1. /*
  2. * Copyright (C) 2007 by Ole Reinhardt, EmbeddedIT. ole.reinhardt@embedded-it.de
  3. * All rights reserved.
  4. *
  5. * This file is based on at91_udp.h
  6. * (c) Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. *
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions and the following disclaimer.
  14. * 2. Redistributions in binary form must reproduce the above copyright
  15. * notice, this list of conditions and the following disclaimer in the
  16. * documentation and/or other materials provided with the distribution.
  17. * 3. Neither the name of the copyright holders nor the names of
  18. * contributors may be used to endorse or promote products derived
  19. * from this software without specific prior written permission.
  20. *
  21. * THIS SOFTWARE IS PROVIDED BY EMBEDDED-IT AND CONTRIBUTORS
  22. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EMBEDDED-IT
  25. * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  26. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  27. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  28. * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  29. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  30. * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  31. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. * For additional information see http://www.ethernut.de/
  34. */
  35. #ifndef _ARCH_ARM_AT91_UDP_H_
  36. #define _ARCH_ARM_AT91_UDP_H_
  37. /*!
  38. * \file arch/arm/at91_udp.h
  39. * \brief AT91 peripherals (USB device port).
  40. *
  41. * \verbatim
  42. * $Id: at91_udp.h 4115 2012-04-12 21:06:13Z olereinhardt $
  43. * \endverbatim
  44. */
  45. /*!
  46. * \addtogroup xgNutArchArmAt91Udp
  47. */
  48. /*@{*/
  49. /*! \name USB Device Port Frame Number Register */
  50. /*@{*/
  51. #define UDP_NUM_OFF 0x00000000 /*!< \brief Frame number register (offset). */
  52. #define UDP_NUM (UDP_BASE + UDP_NUM_OFF) /*!< \brief Frame number register (address). */
  53. #define UDP_FRM_NUM 0x000007FF /*!< \brief Current frame number (mask). */
  54. #define UDP_FRM_NUM_LSB 0 /*!< \brief Current frame number (LSB). */
  55. #define UDP_FRM_ERR _BV(16) /*!< \brief Frame error. */
  56. #define UDP_FRM_OK _BV(17) /*!< \brief Frame OK. */
  57. /*@}*/
  58. /*! \name USB Device Port Global State Register */
  59. /*@{*/
  60. #define UDP_GLB_STAT_OFF 0x00000004 /*!< \brief Global state register (offset). */
  61. #define UDP_GLB_STAT (UDP_BASE + UDP_GLB_STAT_OFF) /*!< \brief Global state register (address). */
  62. #define UDP_FADDEN _BV(0) /*!< \brief Device is in address state. */
  63. #define UDP_CONFG _BV(1) /*!< \brief Device is in configured state. */
  64. #define UDP_ESR _BV(2) /*!< \brief Enable send resume. */
  65. #define UDP_RSMINPR _BV(3) /*!< \brief A resume has been sent to the host. */
  66. #define UDP_RMWUPE _BV(4) /*!< \brief Remote wake up enable. */
  67. /*@}*/
  68. /*! \name USB Device Port Function Address Register */
  69. /*@{*/
  70. #define UDP_FADDR_OFF 0x00000008 /*!< \brief Function address register (offset). */
  71. #define UDP_FADDR (UDP_BASE + UDP_FADDR_OFF) /*!< \brief Function address register (address). */
  72. #define UDP_FADD 0x0000007F /*!< \brief Function address value (mask). */
  73. #define UDP_FADD_LSB 0 /*!< \brief Function address value (LSB). */
  74. #define UDP_FEN _BV(8) /*!< \brief Function endpoint enabled. */
  75. /*@}*/
  76. /*! \name USB Device Port Interrupt Registers */
  77. /*@{*/
  78. #define UDP_IER_OFF 0x00000010 /*!< \brief Interrupt enable register (offset). */
  79. #define UDP_IER (UDP_BASE + UDP_IER_OFF) /*!< \brief Interrupt enable register (address). */
  80. #define UDP_IDR_OFF 0x00000014 /*!< \brief Interrupt disable register (offset). */
  81. #define UDP_IDR (UDP_BASE + UDP_IDR_OFF) /*!< \brief Interrupt disable register (address). */
  82. #define UDP_IMR_OFF 0x00000018 /*!< \brief Interrupt mask register (offset). */
  83. #define UDP_IMR (UDP_BASE + UDP_IMR_OFF) /*!< \brief Interrupt mask register (address). */
  84. #define UDP_ISR_OFF 0x0000001C /*!< \brief Interrupt status register (offset). */
  85. #define UDP_ISR (UDP_BASE + UDP_ISR_OFF) /*!< \brief Interrupt status register (address). */
  86. #define UDP_ICR_OFF 0x00000020 /*!< \brief Interrupt clear register (offset). */
  87. #define UDP_ICR (UDP_BASE + UDP_ICR_OFF) /*!< \brief Interrupt clear register (address). */
  88. #define UDP_EPINT(n) _BV(n) /*!< \brief Endpoint interrupt 0-7. */
  89. #define UDP_RXSUSP _BV(8) /*!< \brief USB suspend interrupt. */
  90. #define UDP_RXRSM _BV(9) /*!< \brief USB resume interrupt. */
  91. #define UDP_EXTRSM _BV(10) /*!< \brief USB external resume interrupt. */
  92. #define UDP_SOFINT _BV(11) /*!< \brief USB start of frame interrupt. */
  93. #define UDP_ENDBUSRES _BV(12) /*!< \brief USB end of bus reset interrupt. */
  94. #define UDP_WAKEUP _BV(13) /*!< \brief USB resume interrupt. */
  95. /*@}*/
  96. /*! \name USB Device Port Reset Endpoint Register */
  97. /*@{*/
  98. #define UDP_RST_EP_OFF 0x00000028 /*!< \brief Reset endpoint register (offset). */
  99. #define UDP_RST_EP (UDP_BASE + UDP_RST_EP_OFF) /*!< \brief Reset endpoint register (address). */
  100. #define UDP_EP(n) _BV(n) /*!< \brief Reset endpoint 0-7. */
  101. /*@}*/
  102. /*! \name USB Device Port Endpoint Control and Status Registers */
  103. /*@{*/
  104. #define UDP_CSR_OFF 0x00000030 /*!< \brief Endpoint control and status register (offset). */
  105. #define UDP_CSR(n) (UDP_BASE + UDP_CSR_OFF + (n) * 4) /*!< \brief Endpoint control and status registers 0-7 (address). */
  106. #define UDP_TXCOMP _BV(0) /*!< \brief Generates an IN packet with data previously written in the DPR. */
  107. #define UDP_RX_DATA_BK0 _BV(1) /*!< \brief Receive data bank 0. */
  108. #define UDP_RXSETUP _BV(2) /*!< \brief Sends Stall to the host (control endpoints). */
  109. #define UDP_STALLSEND_ISOERROR _BV(3) /*!< \brief Stall send / isochronous error (isochronous endpoints). */
  110. #define UDP_TXPKTRDY _BV(4) /*!< \brief Transmit packet ready. */
  111. #define UDP_FORCESTALL _BV(5) /*!< \brief Force Stall (used by control, bulk and isochronous endpoints). */
  112. #define UDP_RX_DATA_BK1 _BV(6) /*!< \brief Receive data bank 1 (only used by endpoints with ping-pong attributes). */
  113. #define UDP_DIR _BV(7) /*!< \brief Transfer direction. */
  114. #define UDP_EPTYPE (0x7 << 8) /*!< \brief Endpoint type mask. */
  115. #define UDP_EPTYPE_CTRL (0x0 << 8) /*!< \brief Endpoint type is control. */
  116. #define UDP_EPTYPE_ISO_OUT (0x1 << 8) /*!< \brief Endpoint type is isochronous output. */
  117. #define UDP_EPTYPE_BULK_OUT (0x2 << 8) /*!< \brief Endpoint type is bulk output. */
  118. #define UDP_EPTYPE_INT_OUT (0x3 << 8) /*!< \brief Endpoint type is interrupt output. */
  119. #define UDP_EPTYPE_ISO_IN (0x5 << 8) /*!< \brief Endpoint type is isochronous input. */
  120. #define UDP_EPTYPE_BULK_IN (0x6 << 8) /*!< \brief Endpoint type is bulk input. */
  121. #define UDP_EPTYPE_INT_IN (0x7 << 8) /*!< \brief Endpoint type is interrupt input. */
  122. #define UDP_DTGLE _BV(11) /*!< \brief Data toggle. */
  123. #define UDP_EPEDS _BV(15) /*!< \brief Endpoint enable disable. */
  124. #define UDP_RXBYTECNT (0x7FF << 16) /*!< \brief Number of bytes available in the FIFO (mask). */
  125. #define UDP_RXBYTECNT_LSB 16 /*!< \brief Number of bytes available in the FIFO (LSB). */
  126. /*@}*/
  127. /*! \name USB Device Port Endpoint FIFO Data Registers */
  128. /*@{*/
  129. #define UDP_FDR_OFF 0x00000050 /*!< \brief Endpoint FIFO data register (offset). */
  130. #define UDP_FDR(n) (UDP_BASE + UDP_FDR_OFF + (n) * 4) /*!< \brief Endpoint FIFO data register (address). */
  131. #define UDP_FIFO_DATA 0x000000FF /*!< \brief FIFO data value (mask). */
  132. #define UDP_FIFO_DATA_LSB 0 /*!< \brief FIFO data value (LSB). */
  133. /*@}*/
  134. /*! \name USB Device Port Tranceiver Control Register */
  135. /*@{*/
  136. #define UDP_TXVC_OFF 0x00000074 /*!< \brief Transceiver control register (offset). */
  137. #define UDP_TXVC (UDP_BASE + UDP_TXVC_OFF) /*!< \brief Transceiver control register (address). */
  138. #define UDP_TXVDIS _BV(8) /*!< \brief Tranceiver disable. */
  139. #define UDP_PUON _BV(9) /*!< \brief Pull-up enable. */
  140. /*@}*/
  141. /*@} xgNutArchArmAt91Udp */
  142. #endif /* _ARCH_ARM_AT91_UDP_H_ */