hwtimer_stm32.h 7.1 KB

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  1. #ifndef _DEV_ARCH_CM3_STM_HWTIMER_STM32_H_
  2. #define _DEV_ARCH_CM3_STM_HWTIMER_STM32_H_
  3. /*
  4. * Copyright (C) 2012 by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)
  5. *
  6. * All rights reserved.
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. *
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions and the following disclaimer.
  14. * 2. Redistributions in binary form must reproduce the above copyright
  15. * notice, this list of conditions and the following disclaimer in the
  16. * documentation and/or other materials provided with the distribution.
  17. * 3. Neither the name of the copyright holders nor the names of
  18. * contributors may be used to endorse or promote products derived
  19. * from this software without specific prior written permission.
  20. *
  21. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  25. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  28. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  31. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32. * SUCH DAMAGE.
  33. *
  34. * For additional information see http://www.ethernut.de/
  35. */
  36. /*
  37. * \verbatim
  38. * $Id: hwtimer_stm32.c 3731 2012-01-12 18:23:31Z olereinhardt $
  39. * \endverbatim
  40. */
  41. #include <stddef.h>
  42. #include <string.h>
  43. #include <cfg/arch.h>
  44. #include <arch/cm3/stm/stm32xxxx.h>
  45. #include <dev/irqreg.h>
  46. #if defined(TIM1_BASE)
  47. #define NUTTIMER1 TIM1_BASE
  48. #endif
  49. #if defined(TIM2_BASE)
  50. #define NUTTIMER2 TIM2_BASE
  51. #endif
  52. #if defined(TIM3_BASE)
  53. #define NUTTIMER3 TIM3_BASE
  54. #endif
  55. #if defined(TIM4_BASE)
  56. #define NUTTIMER4 TIM4_BASE
  57. #endif
  58. #if defined(TIM5_BASE)
  59. #define NUTTIMER5 TIM5_BASE
  60. #endif
  61. #if defined(TIM6_BASE)
  62. #define NUTTIMER6 TIM6_BASE
  63. #endif
  64. #if defined(TIM7_BASE)
  65. #define NUTTIMER7 TIM7_BASE
  66. #endif
  67. #if defined(TIM8_BASE)
  68. #define NUTTIMER8 TIM8_BASE
  69. #endif
  70. #if defined(TIM9_BASE)
  71. #define NUTTIMER9 TIM9_BASE
  72. #endif
  73. #if defined(TIM10_BASE)
  74. #define NUTTIMER10 TIM10_BASE
  75. #endif
  76. #if defined(TIM11_BASE)
  77. #define NUTTIMER11 TIM11_BASE
  78. #endif
  79. #if defined(TIM12_BASE)
  80. #define NUTTIMER12 TIM12_BASE
  81. #endif
  82. #if defined(TIM13_BASE)
  83. #define NUTTIMER13 TIM13_BASE
  84. #endif
  85. #if defined(TIM14_BASE)
  86. #define NUTTIMER14 TIM14_BASE
  87. #endif
  88. #if defined(TIM15_BASE)
  89. #define NUTTIMER15 TIM15_BASE
  90. #endif
  91. #if defined(TIM16_BASE)
  92. #define NUTTIMER16 TIM16_BASE
  93. #endif
  94. #if defined(TIM17_BASE)
  95. #define NUTTIMER17 TIM17_BASE
  96. #endif
  97. #define TIM_Control1( timer ) CM3REG(timer, TIM_TypeDef, CR1 )
  98. #define TIM_Control2( timer ) CM3REG(timer, TIM_TypeDef, CR2 )
  99. #define TIM_AutoReloadValue( timer ) CM3REG(timer, TIM_TypeDef, ARR )
  100. #define TIM_SlaveModeControl( timer ) CM3REG(timer, TIM_TypeDef, SMCR )
  101. #define TIM_DMA_IRQ( timer ) CM3REG(timer, TIM_TypeDef, DIER )
  102. #define TIM_EventGeneration( timer ) CM3REG(timer, TIM_TypeDef, EGR )
  103. #define TIM_CCMode1( timer ) CM3REG(timer, TIM_TypeDef, CCMR1 )
  104. #define TIM_CCMode2( timer ) CM3REG(timer, TIM_TypeDef, CCMR2 )
  105. #define TIM_Prescaler( timer) CM3REG(timer, TIM_TypeDef, PSC )
  106. #define TIM_Compare1( timer) CM3REG(timer, TIM_TypeDef, CCR1)
  107. #define TIM_Compare2( timer) CM3REG(timer, TIM_TypeDef, CCR2)
  108. #define TIM_Compare3( timer) CM3REG(timer, TIM_TypeDef, CCR3)
  109. #define TIM_Compare4( timer) CM3REG(timer, TIM_TypeDef, CCR4)
  110. #define TIM_Counter( timer) CM3REG(timer, TIM_TypeDef, CNT )
  111. #define TIM_Status( timer) CM3REG(timer, TIM_TypeDef, SR )
  112. #define TIM_CCEnable( timer) CM3REG(timer, TIM_TypeDef, CCER )
  113. #define TIM_DMAControl( timer) CM3REG(timer, TIM_TypeDef, DCR )
  114. #define TIM_DMA_Address( timer) CM3REG(timer, TIM_TypeDef, DMAR )
  115. #define TIM_Option( timer) CM3REG(timer, TIM_TypeDef, OR )
  116. #define TIM_Break_Deadtime( timer) CM3REG(timer, TIM_TypeDef, BDTR )
  117. #define TIM_IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_UIE ))
  118. #define TIM_IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_UIE ))
  119. #define TIM_IRQDisable( timer ) CM3BBCLR(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_UIE ))
  120. #define TIM_C1IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC1IE))
  121. #define TIM_C1IRQDisable( timer ) CM3BBCLR(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC1IE))
  122. #define TIM_C2IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC2IE))
  123. #define TIM_C2IRQDisable( timer ) CM3BBCLR(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC2IE))
  124. #define TIM_C3IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC3IE))
  125. #define TIM_C3IRQDisable( timer ) CM3BBCLR(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC3IE))
  126. #define TIM_C4IRQEnable( timer ) CM3BBSET(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC4IE))
  127. #define TIM_C4IRQDisable( timer ) CM3BBCLR(timer, TIM_TypeDef, DIER, _BI16(TIM_DIER_CC4IE))
  128. #define TIM_StartTimer( timer) CM3BBSET(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_CEN ))
  129. #define TIM_StopTimer( timer ) CM3BBCLR(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_CEN ))
  130. #define TIM_OnePulse( timer) CM3BBSET(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_OPM ))
  131. #define TIM_ContPulse( timer) CM3BBCLR(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_OPM ))
  132. #define TIM_AutoReload( timer ) CM3BBSET(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_ARPE ))
  133. #define TIM_NoReload( timer ) CM3BBCLR(timer, TIM_TypeDef, CR1 , _BI16(TIM_CR1_ARPE ))
  134. #define TIM_Update( timer ) CM3BBSET(timer, TIM_TypeDef, EGR , _BI16(TIM_EGR_UG ))
  135. #define TIM_ClearInterruptFlag( timer) CM3BBCLR(timer, TIM_TypeDef, SR , _BI16(TIM_SR_UIF ))
  136. #define TIM_C1ClearInterruptFlag( timer ) CM3BBCLR(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC1IF ))
  137. #define TIM_C2ClearInterruptFlag( timer ) CM3BBCLR(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC2IF ))
  138. #define TIM_C3ClearInterruptFlag( timer ) CM3BBCLR(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC3IF ))
  139. #define TIM_C4ClearInterruptFlag( timer ) CM3BBCLR(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC4IF ))
  140. #define TIM_C1InterruptFlag( timer ) CM3BBGET(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC1IF ))
  141. #define TIM_C2InterruptFlag( timer ) CM3BBGET(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC2IF ))
  142. #define TIM_C3InterruptFlag( timer ) CM3BBGET(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC3IF ))
  143. #define TIM_C4InterruptFlag( timer ) CM3BBGET(timer, TIM_TypeDef, SR , _BI16(TIM_SR_CC4IF ))
  144. #endif