LED back light switch with button press

Makefile

@@ -0,0 +1,93 @@
+TARGET	= ipac
+
+# Application source en include includes
+SRC_DIR	= ./source
+INC_DIR = ./include
+
+# NutOS location (includes and libs)
+NUT_INC = c:/ethernut-4.3.3/nut/include
+NUT_BUILD_INC = c:/ethernut-4.3.3/build/gcc/atmega2561/lib/include
+NUT_LIB_DIR = c:/ethernut-4.3.3/build/gcc/atmega2561/lib
+
+# WinAvr includes
+AVR_INC = c:/winavr/avr/include
+
+
+# Compiler, assembler & linker (flags)
+CC		= 	avr-gcc
+CFLAGS	= 	-mmcu=atmega2561 -Os -Wall -Wstrict-prototypes -DNUT_CPU_FREQ=14745600 \
+			-D__HARVARD_ARCH__ -DNUTOS_VERSION=433 \
+			-Wa,-ahlms=$(SRC_DIR)/$*lst
+ASFLAGS = 	-mmcu=atmega2561 -I. -x assembler-with-cpp -Wa,-ahlms=$(SRC_DIR)/$*lst,-gstabs 
+LDFLAGS	=	-mmcu=atmega2561 -Wl,--defsym=main=0,-Map=TIStreamer.map,--cref
+
+
+# =================================================================================
+# Source files
+CFILES =        main.c			\
+				uart0driver.c	\
+				log.c			\
+                led.c			\
+				keyboard.c		\
+				display.c		\
+                vs10xx.c		\
+                remcon.c		\
+                watchdog.c		\
+				mmc.c			\
+				spidrv.c        \
+                mmcdrv.c        \
+                fat.c			\
+				flash.c			\
+				rtc.c
+			
+				
+# Header files.
+HFILES =        display.h        keyboard.h              \
+                led.h                            \
+                portio.h         remcon.h         log.h          \
+                system.h                 settings.h     \
+                                  inet.h         \
+                platform.h       version.h        update.h       \
+                           uart0driver.h    typedefs.h     \
+                       vs10xx.h         audio.h        \
+                watchdog.h       mmc.h             \
+                flash.h          spidrv.h         command.h      \
+                parse.h          mmcdrv.h         fat.h          \
+                fatdrv.h         flash.h	  	rtc.h
+
+
+# Alle source files in de ./source dir
+SRCS =	$(addprefix $(SRC_DIR)/,$(CFILES))
+OBJS = 	$(SRCS:.c=.o)
+
+NUT_LIBS = $(NUT_LIB_DIR)/nutinit.o -lnutpro -lnutnet -lnutpro -lnutfs -lnutos -lnutdev -lnutarch -lnutnet -lnutcrt -lnutdev
+
+
+# Alle includes (header files) in de ./header dir
+INCS =	$(addprefix $(INC_DIR)/,$(HFILES))
+
+# Linking rule. All *.o to elf file. Then convert to *.hex
+$(TARGET):	$(OBJS)
+	$(CC) $(OBJS) $(LDFLAGS) -L$(NUT_LIB_DIR) $(NUT_LIBS) -o $@.elf
+	avr-objcopy -O ihex $@.elf $@.hex
+#	hex2bin -ebin $@.hex
+
+# Compiling the objs's. avr-gcc autocalls assembler	
+$(SRC_DIR)/%o:	$(SRC_DIR)/%c 
+	$(CC) -c $< $(CFLAGS) -I$(INC_DIR) -I$(NUT_INC) -I$(AVR_INC) -o $@
+
+	
+all: $(TARGET)
+
+debug:
+	
+	@echo $(OBJS)
+
+
+.PHONY: clean
+clean:
+	-rm -f $(OBJS)
+	-rm -f $(SRCS:.c=.lst)
+	-rm -f *.hex *.elf *.map *.bin
+
+

include/arch/arm.h

@@ -0,0 +1,191 @@
+#ifndef _ARCH_ARM_H_
+#define _ARCH_ARM_H_
+
+/*
+ * Copyright (C) 2001-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: arm.h,v $
+ * Revision 1.17  2007/05/02 11:32:07  haraldkipp
+ * Mapping of Harvard specific stdio functions moved to stdio.h and io.h.
+ *
+ * Revision 1.16  2006/08/31 19:04:08  haraldkipp
+ * Added support for the AT91SAM9260 and Atmel's AT91SAM9260 Evaluation Kit.
+ *
+ * Revision 1.15  2006/08/05 11:58:22  haraldkipp
+ * Missing brackets may result in unexpected expansion of the _BV() macro.
+ *
+ * Revision 1.14  2006/08/01 07:35:59  haraldkipp
+ * Exclude function prototypes when included by assembler.
+ *
+ * Revision 1.13  2006/07/21 09:08:58  haraldkipp
+ * Map puts_P to puts and _write_P to _write for non-Harvard architectures.
+ *
+ * Revision 1.12  2006/07/10 14:27:03  haraldkipp
+ * C++ will use main instead of NutAppMain. Contributed by Matthias Wilde.
+ *
+ * Revision 1.11  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * Revision 1.10  2006/06/28 17:22:34  haraldkipp
+ * Make it compile for AT91SAM7X256.
+ *
+ * Revision 1.9  2006/05/25 09:35:27  haraldkipp
+ * Dummy macros added to support the avr-libc special function register
+ * definitions.
+ *
+ * Revision 1.8  2006/03/16 15:25:26  haraldkipp
+ * Changed human readable strings from u_char to char to stop GCC 4 from
+ * nagging about signedness.
+ *
+ * Revision 1.7  2006/03/02 20:02:05  haraldkipp
+ * Added a few macros to allow compilation with ICCARM.
+ *
+ * Revision 1.6  2006/02/23 15:34:00  haraldkipp
+ * Support for Philips LPC2xxx Family and LPC-E2294 Board from Olimex added.
+ * Many thanks to Michael Fischer for this port.
+ *
+ * Revision 1.5  2005/11/20 14:45:15  haraldkipp
+ * Define printf_P for non Harvard architectures.
+ *
+ * Revision 1.4  2005/10/24 18:03:02  haraldkipp
+ * GameBoy header file added.
+ *
+ * Revision 1.3  2005/10/24 10:35:05  haraldkipp
+ * Port I/O macros added.
+ *
+ * Revision 1.2  2004/09/08 10:24:26  haraldkipp
+ * RAMSTART is too platform dependant
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ * Revision 1.1  2004/02/01 18:49:47  haraldkipp
+ * Added CPU family support
+ *
+ */
+
+#include <cfg/arch.h>
+#if defined (MCU_AT91R40008) || defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM9260)
+#include <arch/arm/at91.h>
+#elif defined (MCU_GBA)
+#include <arch/arm/gba.h>
+#elif defined (MCU_LPC2XXX)
+#include <arch/arm/lpc2xxx.h>
+#endif
+
+#ifndef __ASSEMBLER__
+#include <dev/mweeprom.h>
+#endif
+
+#define ARM_MODE_USER       0x10
+#define ARM_MODE_FIQ        0x11
+#define ARM_MODE_IRQ        0x12
+#define ARM_MODE_SVC        0x13
+#define ARM_MODE_ABORT      0x17
+#define ARM_MODE_UNDEF      0x1B
+#define ARM_MODE_SYS        0x1F
+#define ARM_MODE_MASK       0x1F
+
+#define I_BIT               0x80
+#define F_BIT               0x40
+#define T_BIT               0x20
+
+#ifdef __GNUC__
+#define CONST      const
+#define INLINE     inline
+#else
+#ifndef CONST
+#define CONST      const
+#endif
+#ifndef INLINE
+#define INLINE
+#endif
+#endif
+
+#define PSTR(p)    (p)
+#define PRG_RDB(p) (*((const char *)(p)))
+
+#define prog_char  const char
+#define PGM_P      prog_char *
+
+#define SIGNAL(x)  __attribute__((interrupt_handler)) void x(void)
+#define RAMFUNC __attribute__ ((long_call, section (".ramfunc")))
+
+#if !defined(__arm__) && !defined(__cplusplus)
+#define main       NutAppMain
+#endif
+
+#define strlen_P(x)             strlen((char *)(x))
+#define strcpy_P(x,y)           strcpy(x,(char *)(y))
+
+#define strcmp_P(x, y)          strcmp((char *)(x), (char *)(y))
+#define memcpy_P(x, y, z)       memcpy(x, y, z)
+
+#ifndef __ASSEMBLER__
+/*!
+ * \brief End of uninitialised data segment. Defined in the linker script.
+ */
+extern void *__bss_end;
+
+/*!
+ * \brief Begin of the stack segment. Defined in the linker script.
+ */
+extern void *__stack;
+#endif
+
+#ifndef _NOP
+#ifdef __GNUC__
+#define _NOP() __asm__ __volatile__ ("mov r0, r0")
+#else
+#define _NOP() asm("mov r0, r0")
+#endif
+#endif
+
+#define outb(_reg, _val)  (*((volatile unsigned char *)(_reg)) = (_val))
+#define outw(_reg, _val)  (*((volatile unsigned short *)(_reg)) = (_val))
+#define outr(_reg, _val)  (*((volatile unsigned int *)(_reg)) = (_val))
+
+#define inb(_reg)   (*((volatile unsigned char *)(_reg)))
+#define inw(_reg)   (*((volatile unsigned short *)(_reg)))
+#define inr(_reg)   (*((volatile unsigned int *)(_reg)))
+
+#define _BV(bit)    (1 << (bit))
+
+#ifdef __IMAGECRAFT__
+#define __attribute__(x)
+#endif
+
+#define _SFR_MEM8(addr)     (addr)
+#define _SFR_MEM16(addr)    (addr)
+
+#endif

include/arch/arm/at91.h

@@ -0,0 +1,166 @@
+#ifndef _ARCH_ARM_AT91_H_
+#define _ARCH_ARM_AT91_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91.h,v $
+ * Revision 1.10  2006/08/31 19:04:08  haraldkipp
+ * Added support for the AT91SAM9260 and Atmel's AT91SAM9260 Evaluation Kit.
+ *
+ * Revision 1.9  2006/08/01 07:35:59  haraldkipp
+ * Exclude function prototypes when included by assembler.
+ *
+ * Revision 1.8  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * Revision 1.7  2006/06/28 17:22:34  haraldkipp
+ * Make it compile for AT91SAM7X256.
+ *
+ * Revision 1.6  2006/05/25 09:09:57  haraldkipp
+ * API documentation updated and corrected.
+ *
+ * Revision 1.5  2006/04/07 12:57:00  haraldkipp
+ * Fast interrupt doesn't require to store R8-R12.
+ *
+ * Revision 1.4  2006/03/02 20:02:56  haraldkipp
+ * Added ICCARM interrupt entry code. Probably not working, because I
+ * excluded an immediate load.
+ *
+ * Revision 1.3  2006/01/05 16:52:49  haraldkipp
+ * Baudrate calculation is now based on NutGetCpuClock().
+ * The AT91_US_BAUD macro had been marked deprecated.
+ *
+ * Revision 1.2  2005/11/20 14:44:14  haraldkipp
+ * Register offsets added.
+ *
+ * Revision 1.1  2005/10/24 10:31:13  haraldkipp
+ * Moved from parent directory.
+ *
+ *
+ * \endverbatim
+ */
+
+#if defined (MCU_AT91R40008)
+#include <arch/arm/at91x40.h>
+#elif defined (MCU_AT91SAM7X256)
+#include <arch/arm/at91sam7x.h>
+#elif defined (MCU_AT91SAM9260)
+#include <arch/arm/at91sam9260.h>
+#endif
+
+/*! \addtogroup xgNutArchArmAt91 */
+/*@{*/
+
+#ifdef __GNUC__
+
+/*!
+ * \brief Interrupt entry.
+ */
+#define IRQ_ENTRY() \
+    asm volatile("sub   lr, lr,#4"          "\n\t"  /* Adjust LR */ \
+                 "stmfd sp!,{r0-r12,lr}"    "\n\t"  /* Save registers on IRQ stack. */ \
+                 "mrs   r1, spsr"           "\n\t"  /* Save SPSR */ \
+                 "stmfd sp!,{r1}"           "\n\t")     /* */
+
+/*!
+ * \brief Interrupt exit.
+ */
+#define IRQ_EXIT() \
+    asm volatile("ldmfd sp!, {r1}"          "\n\t"  /* Restore SPSR */ \
+                 "msr   spsr_c, r1"         "\n\t"  /* */ \
+                 "ldr   r0, =0xFFFFF000"    "\n\t"  /* End of interrupt. */ \
+                 "str   r0, [r0, #0x130]"   "\n\t"  /* */ \
+                 "ldmfd sp!, {r0-r12, pc}^" "\n\t")     /* Restore registers and return. */
+
+/*!
+ * \brief Fast interrupt entry.
+ */
+#define FIQ_ENTRY() \
+    asm volatile("sub   lr, lr,#4"          "\n\t"  /* Adjust LR */ \
+                 "stmfd sp!,{r0-r7,lr}"    "\n\t"  /* Save registers on IRQ stack. */ \
+                 "mrs   r1, spsr"           "\n\t"  /* Save SPSR */ \
+                 "stmfd sp!,{r1}"           "\n\t")     /* */
+
+/*!
+ * \brief Fast interrupt exit.
+ */
+#define FIQ_EXIT() \
+    asm volatile("ldmfd sp!, {r1}"          "\n\t"  /* Restore SPSR */ \
+                 "msr   spsr_c, r1"         "\n\t"  /* */ \
+                 "ldr   r0, =0xFFFFF000"    "\n\t"  /* End of interrupt. */ \
+                 "str   r0, [r0, #0x130]"   "\n\t"  /* */ \
+                 "ldmfd sp!, {r0-r7, pc}^" "\n\t")     /* Restore registers and return. */
+
+#else /* __IMAGECRAFT__ */
+
+#define IRQ_ENTRY() \
+    asm("sub   lr, lr,#4\n" \
+        "stmfd sp!,{r0-r12,lr}\n" \
+        "mrs   r1, spsr\n" \
+        "stmfd sp!,{r1}\n")
+
+#define IRQ_EXIT() \
+    asm("ldmfd sp!, {r1}\n" \
+        "msr   spsr_c, r1\n" \
+        ";ldr   r0, =0xFFFFF000\n" /* ICCARM: FIXME! */ \
+        "str   r0, [r0, #0x130]\n" \
+        "ldmfd sp!, {r0-r12, pc}^")
+
+#define FIQ_ENTRY() \
+    asm("sub   lr, lr,#4\n" \
+        "stmfd sp!,{r0-r7,lr}\n" \
+        "mrs   r1, spsr\n" \
+        "stmfd sp!,{r1}\n")
+
+#define FIQ_EXIT() \
+    asm("ldmfd sp!, {r1}\n" \
+        "msr   spsr_c, r1\n" \
+        ";ldr   r0, =0xFFFFF000\n" /* ICCARM: FIXME! */ \
+        "str   r0, [r0, #0x130]\n" \
+        "ldmfd sp!, {r0-r7, pc}^")
+
+#endif
+
+/*@} xgNutArchArmAt91 */
+
+#ifndef __ASSEMBLER__
+extern void McuInit(void);
+#endif
+
+#endif                          /* _ARCH_ARM_AT91_H_ */

include/arch/arm/at91_aic.h

@@ -0,0 +1,197 @@
+#ifndef _ARCH_ARM_AT91_AIC_H_
+#define _ARCH_ARM_AT91_AIC_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_aic.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_aic.h,v $
+ * Revision 1.2  2006/08/31 19:08:14  haraldkipp
+ * Defining register offsets simplifies assembly programming.
+ *
+ * Revision 1.1  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Aic
+ */
+/*@{*/
+
+/*! \name Interrupt Source Mode Registers */
+/*@{*/
+/*! \brief Source mode register array.
+ */
+#define AIC_SMR(i)  (AIC_BASE + i * 4)
+
+/*! \brief Priority mask. 
+ *
+ * Priority levels can be between 0 (lowest) and 7 (highest).
+ */
+#define AIC_PRIOR                       0x00000007
+
+/*! \brief Interrupt source type mask. 
+ *
+ * Internal interrupts can level sensitive or edge triggered.
+ *
+ * External interrupts can triggered on positive or negative levels or 
+ * on rising or falling edges.
+ */
+#define AIC_SRCTYPE                     0x00000060
+
+#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000      /*!< \brief Internal level sensitive. */
+#define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x00000020      /*!< \brief Internal edge triggered. */
+#define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00000000      /*!< \brief External low level. */
+#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020      /*!< \brief External falling edge. */
+#define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x00000040      /*!< \brief External high level. */
+#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060      /*!< \brief External rising edge. */
+/*@}*/
+
+/*! \name Interrupt Source Vector Registers */
+/*@{*/
+/*! \brief Source vector register array. 
+ *
+ * Stores the addresses of the corresponding interrupt handlers.
+ */
+#define AIC_SVR(i)  (AIC_BASE + 0x80 + i * 4)
+/*@}*/
+
+/*! \name Interrupt Vector Register */
+/*@{*/
+#define AIC_IVR_OFF                 0x00000100  /*!< \brief IRQ vector register offset. */
+#define AIC_IVR     (AIC_BASE + AIC_IVR_OFF)    /*!< \brief IRQ vector register address. */
+/*@}*/
+
+/*! \name Fast Interrupt Vector Register */
+/*@{*/
+#define AIC_FVR_OFF                 0x00000104  /*!< \brief FIQ vector register offset. */
+#define AIC_FVR     (AIC_BASE + AIC_FVR_OFF)    /*!< \brief FIQ vector register address. */
+/*@}*/
+
+/*! \name Interrupt Status Register */
+/*@{*/
+#define AIC_ISR_OFF                 0x00000108  /*!< \brief Interrupt status register offset. */
+#define AIC_ISR     (AIC_BASE + AIC_ISR_OFF)    /*!< \brief Interrupt status register address. */
+#define AIC_IRQID                   0x0000001F  /*!< \brief Current interrupt identifier mask. */
+/*@}*/
+
+/*! \name Interrupt Pending Register */
+/*@{*/
+#define AIC_IPR_OFF                 0x0000010C  /*!< \brief Interrupt pending register offset. */
+#define AIC_IPR     (AIC_BASE + AIC_IPR_OFF)    /*!< \brief Interrupt pending register address. */
+/*@}*/
+
+/*! \name Interrupt Mask Register */
+/*@{*/
+#define AIC_IMR_OFF                 0x00000110  /*!< \brief Interrupt mask register offset. */
+#define AIC_IMR     (AIC_BASE + AIC_IMR_OFF)    /*!< \brief Interrupt mask register address. */
+/*@}*/
+
+/*! \name Interrupt Core Status Register */
+/*@{*/
+#define AIC_CISR_OFF                0x00000114  /*!< \brief Core interrupt status register offset. */
+#define AIC_CISR    (AIC_BASE + AIC_CISR_OFF)   /*!< \brief Core interrupt status register address. */
+#define AIC_NFIQ                    0x00000001  /*!< \brief Core FIQ Status */
+#define AIC_NIRQ                    0x00000002  /*!< \brief Core IRQ Status */
+/*@}*/
+
+/*! \name Interrupt Enable Command Register */
+/*@{*/
+#define AIC_IECR_OFF                0x00000120  /*!< \brief Interrupt enable command register offset. */
+#define AIC_IECR    (AIC_BASE + AIC_IECR_OFF)   /*!< \brief Interrupt enable command register address. */
+/*@}*/
+
+/*! \name Interrupt Disable Command Register */
+/*@{*/
+#define AIC_IDCR_OFF                0x00000124  /*!< \brief Interrupt disable command register offset. */
+#define AIC_IDCR    (AIC_BASE + AIC_IDCR_OFF)   /*!< \brief Interrupt disable command register address. */
+/*@}*/
+
+/*! \name Interrupt Clear Command Register */
+/*@{*/
+#define AIC_ICCR_OFF                0x00000128  /*!< \brief Interrupt clear command register offset. */
+#define AIC_ICCR    (AIC_BASE + AIC_ICCR_OFF)   /*!< \brief Interrupt clear command register address. */
+/*@}*/
+
+/*! \name Interrupt Set Command Register */
+/*@{*/
+#define AIC_ISCR_OFF                0x0000012C  /*!< \brief Interrupt set command register offset. */
+#define AIC_ISCR    (AIC_BASE + AIC_ISCR_OFF)   /*!< \brief Interrupt set command register address. */
+/*@}*/
+
+/*! \name End Of Interrupt Command Register */
+/*@{*/
+#define AIC_EOICR_OFF               0x00000130  /*!< \brief End of interrupt command register offset. */
+#define AIC_EOICR   (AIC_BASE + AIC_EOICR_OFF)  /*!< \brief End of interrupt command register address. */
+/*@}*/
+
+/*! \name Spurious Interrupt Vector Register */
+/*@{*/
+#define AIC_SPU_OFF                 0x00000134  /*!< \brief Spurious vector register offset. */
+#define AIC_SPU     (AIC_BASE + AIC_SPU_OFF)    /*!< \brief Spurious vector register address. */
+/*@}*/
+
+/*! \name Debug Control Register */
+/*@{*/
+#define AIC_DCR_OFF                 0x0000138   /*!< \brief Debug control register offset. */
+#define AIC_DCR     (AIC_BASE + AIC_DCR_OFF)    /*!< \brief Debug control register address. */
+/*@}*/
+
+/*! \name Fast Forcing Enable Register */
+/*@{*/
+#define AIC_FFER_OFF                0x00000140  /*!< \brief Fast forcing enable register offset. */
+#define AIC_FFER    (AIC_BASE + AIC_FFER_OFF)   /*!< \brief Fast forcing enable register address. */
+/*@}*/
+
+/*! \name Fast Forcing Disable Register */
+/*@{*/
+#define AIC_FFDR_OFF                0x00000144  /*!< \brief Fast forcing disable register address. */
+#define AIC_FFDR    (AIC_BASE + AIC_FFDR_OFF)   /*!< \brief Fast forcing disable register address. */
+/*@}*/
+
+/*! \name Fast Forcing Status Register */
+/*@{*/
+#define AIC_FFSR_OFF                0x00000148  /*!< \brief Fast forcing status register address. */
+#define AIC_FFSR    (AIC_BASE + AIC_FFSR_OFF)   /*!< \brief Fast forcing status register address. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Aic */
+
+#endif                          /* _ARCH_ARM_AT91_AIC_H_ */

include/arch/arm/at91_ccfg.h

@@ -0,0 +1,70 @@
+#ifndef _ARCH_ARM_AT91_CCFG_H_
+#define _ARCH_ARM_AT91_CCFG_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_ccfg.h
+ * \brief AT91 chip configuration.
+ *
+ * \verbatim
+ *
+ * $Log: at91_ccfg.h,v $
+ * Revision 1.1  2006/08/31 19:10:37  haraldkipp
+ * New peripheral register definitions for the AT91SAM9260.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Ccfg
+ */
+/*@{*/
+
+
+/*! \name Chip Select Assignment Register */
+/*@{*/
+#define CCFG_CSA_OFF                0x0000000C  /*!< \brief Chip select assignment register offset. */
+#define CCFG_CSA    (CCFG_BASE + CCFG_CSA_OFF)  /*!< \brief Chip select assignment register address. */
+#define CCFG_CS1A                   0x00000002  /*!< \brief SDRAM at chip select 1. */
+#define CCFG_CS3A                   0x00000008  /*!< \brief SmartMedia at chip select 3. */
+#define CCFG_CS4A                   0x00000010  /*!< \brief First CompactFlash slot at chip select 4. */
+#define CCFG_CS5A                   0x00000020  /*!< \brief Second CompactFlash slot at chip select 5. */
+#define CCFG_DBPUC                  0x00000100  /*!< \brief Data bus pull-ups disabled. */
+#define CCFG_VDDIOMSEL              0x00010000  /*!< \brief 3.3V memory. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Ccfg */
+
+#endif                          /* _ARCH_ARM_AT91_CCFG_H_ */

include/arch/arm/at91_dbgu.h

@@ -0,0 +1,92 @@
+#ifndef _ARCH_ARM_AT91_DBGU_H_
+#define _ARCH_ARM_AT91_DBGU_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_dbgu.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_dbgu.h,v $
+ * Revision 1.2  2006/08/05 11:54:45  haraldkipp
+ * PDC registers added.
+ *
+ * Revision 1.1  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Dbgu
+ */
+/*@{*/
+
+#define DBGU_CR     (DBGU_BASE + US_CR_OFF)     /*!< \brief DBGU control register address. */
+#define DBGU_MR     (DBGU_BASE + US_MR_OFF)     /*!< \brief DBGU mode register address. */
+#define DBGU_IER    (DBGU_BASE + US_IER_OFF)    /*!< \brief DBGU interrupt enable register address. */
+#define DBGU_IDR    (DBGU_BASE + US_IDR_OFF)    /*!< \brief DBGU interrupt disable register address. */
+#define DBGU_IMR    (DBGU_BASE + US_IMR_OFF)    /*!< \brief DBGU interrupt mask register address. */
+#define DBGU_SR     (DBGU_BASE + US_CSR_OFF)    /*!< \brief DBGU status register address. */
+#define DBGU_RHR    (DBGU_BASE + US_RHR_OFF)    /*!< \brief DBGU receiver holding register address. */
+#define DBGU_THR    (DBGU_BASE + US_THR_OFF)    /*!< \brief DBGU transmitter holding register address. */
+#define DBGU_BRGR   (DBGU_BASE + US_BRGR_OFF)   /*!< \brief DBGU baud rate register address. */
+
+#define DBGU_CIDR_OFF           0x00000040      /*!< \brief DBGU chip ID register offset. */
+#define DBGU_CIDR   (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
+
+#define DBGU_EXID_OFF           0x00000044      /*!< \brief DBGU chip ID extension register offset. */
+#define DBGU_EXID   (DBGU_BASE + DBGU_EXID_OFF) /*!< \brief DBGU chip ID extension register. */
+
+#define DBGU_FNR_OFF            0x00000048      /*!< \brief DBGU force NTRST register offset. */
+#define DBGU_FNR    (DBGU_BASE + DBGU_FNR_OFF)  /*!< \brief DBGU force NTRST register. */
+
+#if defined(DBGU_HAS_PDC)
+#define DBGU_RPR    (DBGU_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC receive pointer register. */
+#define DBGU_RCR    (DBGU_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC receive counter register. */
+#define DBGU_TPR    (DBGU_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC transmit pointer register. */
+#define DBGU_TCR    (DBGU_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC transmit counter register. */
+#define DBGU_RNPR   (DBGU_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC receive next pointer register. */
+#define DBGU_RNCR   (DBGU_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC receive next counter register. */
+#define DBGU_TNPR   (DBGU_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC transmit next pointer register. */
+#define DBGU_TNCR   (DBGU_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC transmit next counter register. */
+#define DBGU_PTCR   (DBGU_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC transfer control register. */
+#define DBGU_PTSR   (DBGU_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC transfer status register. */
+#endif
+
+/*@} xgNutArchArmAt91Dbgu */
+
+#endif                          /* _ARCH_ARM_AT91_DBGU_H_ */

include/arch/arm/at91_ebi.h

@@ -0,0 +1,123 @@
+#ifndef _ARCH_ARM_AT91_EBI_H_
+#define _ARCH_ARM_AT91_EBI_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_ebi.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_ebi.h,v $
+ * Revision 1.1  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Ebi
+ */
+/*@{*/
+
+/*! \name Chip Select Register */
+/*@{*/
+#define EBI_CSR(i)      (EBI_BASE + i * 4)      /*!< \brief Chip select register address. */
+
+#define EBI_DBW                 0x00000003      /*!< \brief Masks data bus width. */
+#define EBI_DBW_16              0x00000001      /*!< \brief 16-bit data bus width. */
+#define EBI_DBW_8               0x00000002      /*!< \brief 8-bit data bus width. */
+
+#define EBI_NWS                 0x0000001C      /*!< \brief Masks number of wait states. */
+#define EBI_NWS_1               0x00000000      /*!< \brief 1 wait state. */
+#define EBI_NWS_2               0x00000004      /*!< \brief 2 wait states. */
+#define EBI_NWS_3               0x00000008      /*!< \brief 3 wait states. */
+#define EBI_NWS_4               0x0000000C      /*!< \brief 4 wait states. */
+#define EBI_NWS_5               0x00000010      /*!< \brief 5 wait states. */
+#define EBI_NWS_6               0x00000014      /*!< \brief 6 wait states. */
+#define EBI_NWS_7               0x00000018      /*!< \brief 7 wait states. */
+#define EBI_NWS_8               0x0000001C      /*!< \brief 8 wait states. */
+
+#define EBI_WSE                 0x00000020      /*!< \brief Wait state enable. */
+
+#define EBI_PAGES               0x00000180      /*!< \brief Page size mask. */
+#define EBI_PAGES_1M            0x00000000      /*!< \brief 1 MByte page size. */
+#define EBI_PAGES_4M            0x00000080      /*!< \brief 4 MBytes page size. */
+#define EBI_PAGES_16M           0x00000100      /*!< \brief 16 MBytes page size. */
+#define EBI_PAGES_64M           0x00000180      /*!< \brief 64 MBytes page size. */
+
+#define EBI_TDF                 0x00000E00      /*!< \brief Masks data float output time clock cycles. */
+#define EBI_TDF_0               0x00000000      /*!< \brief No added cycles. */
+#define EBI_TDF_1               0x00000200      /*!< \brief 1 cycle. */
+#define EBI_TDF_2               0x00000400      /*!< \brief 2 cycles. */
+#define EBI_TDF_3               0x00000600      /*!< \brief 3 cycles. */
+#define EBI_TDF_4               0x00000800      /*!< \brief 4 cycles. */
+#define EBI_TDF_5               0x00000A00      /*!< \brief 5 cycles. */
+#define EBI_TDF_6               0x00000C00      /*!< \brief 6 cycles. */
+#define EBI_TDF_7               0x00000E00      /*!< \brief 7 cycles. */
+
+#define EBI_BAT                 0x00001000      /*!< \brief Byte access type */
+#define EBI_BAT_BYTE_WRITE      0x00000000      /*!< \brief Byte write access type */
+#define EBI_BAT_BYTE_SELECT     0x00001000      /*!< \brief Byte select access type */
+
+#define EBI_CSEN                0x00002000      /*!< \brief Chip select enable */
+
+#define EBI_BA                  0xFFF00000      /*!< \brief Page base address mask. */
+/*@}*/
+
+/*! \name Remap Control Register */
+/*@{*/
+#define EBI_RCR         (EBI_BASE + 0x20)       /*!< \brief Remap control register address. */
+#define EBI_RCB                 0x00000001      /*!< \brief Remap command. */
+/*@}*/
+
+/*! \name Memory Control Register */
+/*@{*/
+#define EBI_MCR         (EBI_BASE + 0x24)       /*!< \brief Memory control register address. */
+#define EBI_ALE                 0x00000007      /*!< \brief Address line enable */
+#define EBI_ALE_16M             0x00000000      /*!< \brief 16 Mbytes total address space. */
+#define EBI_ALE_8M              0x00000004      /*!< \brief 8 Mbytes total address space. */
+#define EBI_ALE_4M              0x00000005      /*!< \brief 4 Mbytes total address space. */
+#define EBI_ALE_2M              0x00000006      /*!< \brief 2 Mbytes total address space. */
+#define EBI_ALE_1M              0x00000007      /*!< \brief 1 Mbyte total address space. */
+
+#define EBI_DRP                 0x00000010      /*!< \brief Data read protocol mask. */
+#define EBI_DRP_STANDARD        0x00000000      /*!< \brief Standard read protocol. */
+#define EBI_DRP_EARLY           0x00000010      /*!< \brief Early read protocol. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Ebi */
+
+#endif                          /* _ARCH_ARM_AT91_EBI_H_ */

include/arch/arm/at91_efc.h

@@ -0,0 +1,61 @@
+#ifndef _ARCH_ARM_AT91_EFC_H_
+#define	_ARCH_ARM_AT91_EFC_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: at91_efc.h,v $
+ * Revision 1.1  2006/07/26 11:20:57  haraldkipp
+ * Added non-volatile configuration memory support for SAM7X, using upper
+ * 16k region of on-chip flash.
+ *
+ */
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+/* Prototypes */
+
+extern int At91EfcSectorErase(u_int off);
+extern int At91EfcSectorRead(u_int off, void *data, u_int len);
+extern int At91EfcSectorWrite(u_int off, CONST void *data, u_int len);
+
+extern int At91EfcRegionLock(u_int off);
+extern int At91EfcRegionUnlock(u_int off);
+
+extern int At91EfcParamRead(u_int pos, void *data, u_int len);
+extern int At91EfcParamWrite(u_int pos, CONST void *data, u_int len);
+
+__END_DECLS
+/* End of prototypes */
+#endif

include/arch/arm/at91_emac.h

@@ -0,0 +1,309 @@
+#ifndef _ARCH_ARM_AT91_EMAC_H_
+#define _ARCH_ARM_AT91_EMAC_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_emac.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_emac.h,v $
+ * Revision 1.2  2006/08/31 19:19:55  haraldkipp
+ * No time to write comments. ;-)
+ *
+ * Revision 1.1  2006/07/05 07:45:25  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Emac
+ */
+/*@{*/
+
+/*! \name Network Control Register */
+/*@{*/
+#define EMAC_NCR_OFF                0x00000000  /*!< \brief Network control register offset. */
+#define EMAC_NCR    (EMAC_BASE + EMAC_NCR_OFF)  /*!< \brief Network Control register address. */
+
+#define EMAC_LB                     0x00000001  /*!< \brief PHY loopback. */
+#define EMAC_LLB                    0x00000002  /*!< \brief EMAC loopback. */
+#define EMAC_RE                     0x00000004  /*!< \brief Receive enable. */
+#define EMAC_TE                     0x00000008  /*!< \brief Transmit enable. */
+#define EMAC_MPE                    0x00000010  /*!< \brief Management port enable. */
+#define EMAC_CLRSTAT                0x00000020  /*!< \brief Clear statistics registers. */
+#define EMAC_INCSTAT                0x00000040  /*!< \brief Increment statistics registers. */
+#define EMAC_WESTAT                 0x00000080  /*!< \brief Write enable for statistics registers. */
+#define EMAC_BP                     0x00000100  /*!< \brief Back pressure. */
+#define EMAC_TSTART                 0x00000200  /*!< \brief Start Transmission. */
+#define EMAC_THALT                  0x00000400  /*!< \brief Transmission halt. */
+#define EMAC_TPFR                   0x00000800  /*!< \brief Transmit pause frame. */
+#define EMAC_TZQ                    0x00001000  /*!< \brief Transmit zero quantum pause frame. */
+/*@}*/
+
+/*! \name Network Configuration Register */
+/*@{*/
+#define EMAC_NCFGR_OFF              0x00000004  /*!< \brief Network configuration register offset. */
+#define EMAC_NCFGR (EMAC_BASE + EMAC_NCFGR_OFF) /*!< \brief Network configuration register address. */
+
+#define EMAC_SPD                    0x00000001  /*!< \brief Speed, set for 100Mb. */
+#define EMAC_FD                     0x00000002  /*!< \brief Full duplex. */
+#define EMAC_JFRAME                 0x00000008  /*!< \brief Jumbo Frames. */
+#define EMAC_CAF                    0x00000010  /*!< \brief Copy all frames. */
+#define EMAC_NBC                    0x00000020  /*!< \brief No broadcast. */
+#define EMAC_MTI                    0x00000040  /*!< \brief Multicast hash event enable. */
+#define EMAC_UNI                    0x00000080  /*!< \brief Unicast hash enable. */
+#define EMAC_BIG                    0x00000100  /*!< \brief Receive 1522 bytes. */
+#define EMAC_EAE                    0x00000200  /*!< \brief External address match enable. */
+#define EMAC_CLK                    0x00000C00  /*!< \brief Clock divider mask. */
+#define EMAC_CLK_HCLK_8             0x00000000  /*!< \brief HCLK divided by 8. */
+#define EMAC_CLK_HCLK_16            0x00000400  /*!< \brief HCLK divided by 16. */
+#define EMAC_CLK_HCLK_32            0x00000800  /*!< \brief HCLK divided by 32. */
+#define EMAC_CLK_HCLK_64            0x00000C00  /*!< \brief HCLK divided by 64. */
+#define EMAC_RTY                    0x00001000  /*!< \brief Retry test. */
+#define EMAC_PAE                    0x00002000  /*!< \brief Pause enable. */
+#define EMAC_RBOF                   0x0000C000  /*!< \brief Receive buffer offset. */
+#define EMAC_RBOF_OFFSET_0          0x00000000  /*!< \brief No offset from start of receive buffer. */
+#define EMAC_RBOF_OFFSET_1          0x00004000  /*!< \brief One byte offset from start of receive buffer. */
+#define EMAC_RBOF_OFFSET_2          0x00008000  /*!< \brief Two bytes offset from start of receive buffer. */
+#define EMAC_RBOF_OFFSET_3          0x0000C000  /*!< \brief Three bytes offset from start of receive buffer. */
+#define EMAC_RLCE                   0x00010000  /*!< \brief Receive length field checking enable. */
+#define EMAC_DRFCS                  0x00020000  /*!< \brief Discard receive FCS. */
+#define EMAC_EFRHD                  0x00040000  /*!< \brief Allow receive during transmit in half duplex. */
+#define EMAC_IRXFCS                 0x00080000  /*!< \brief Ignore received FCS. */
+/*@}*/
+
+/*! \name Network Status Register */
+/*@{*/
+#define EMAC_NSR_OFF                0x00000008  /*!< \brief Network Status register offset. */
+#define EMAC_NSR    (EMAC_BASE + EMAC_NSR_OFF)  /*!< \brief Network Status register address. */
+#define EMAC_LINKR                  0x00000001  /*!< \brief . */
+#define EMAC_MDIO                   0x00000002  /*!< \brief Status of MDIO input pin. */
+#define EMAC_IDLE                   0x00000004  /*!< \brief Set when PHY is running. */
+/*@}*/
+
+/*! \name Transmit Status Register */
+/*@{*/
+#define EMAC_TSR_OFF                0x00000014  /*!< \brief Transmit Status register offset. */
+#define EMAC_TSR    (EMAC_BASE + EMAC_TSR_OFF)  /*!< \brief Transmit Status register address. */
+
+#define EMAC_UBR                    0x00000001  /*!< \brief Used bit read. */
+#define EMAC_COL                    0x00000002  /*!< \brief Collision occurred. */
+#define EMAC_RLES                   0x00000004  /*!< \brief Retry limit exceeded. */
+#define EMAC_TGO                    0x00000008  /*!< \brief Transmit active. */
+#define EMAC_BEX                    0x00000010  /*!< \brief Buffers exhausted mid frame. */
+#define EMAC_COMP                   0x00000020  /*!< \brief Transmit complete. */
+#define EMAC_UND                    0x00000040  /*!< \brief Transmit underrun. */
+/*@}*/
+
+/*! \name Buffer Queue Pointer Register */
+/*@{*/
+#define EMAC_RBQP_OFF               0x00000018  /*!< \brief Receive buffer queue pointer. */
+#define EMAC_RBQP   (EMAC_BASE + EMAC_RBQP_OFF) /*!< \brief Receive buffer queue pointer. */
+#define EMAC_TBQP_OFF               0x0000001C  /*!< \brief Transmit buffer queue pointer. */
+#define EMAC_TBQP   (EMAC_BASE + EMAC_TBQP_OFF) /*!< \brief Transmit buffer queue pointer. */
+/*@}*/
+
+/*! \name Receive Status Register */
+/*@{*/
+#define EMAC_RSR_OFF                0x00000020  /*!< \brief Receive status register offset. */
+#define EMAC_RSR    (EMAC_BASE + EMAC_RSR_OFF)  /*!< \brief Receive status register address. */
+
+#define EMAC_BNA                    0x00000001  /*!< \brief Buffer not available. */
+#define EMAC_REC                    0x00000002  /*!< \brief Frame received. */
+#define EMAC_OVR                    0x00000004  /*!< \brief Receive overrun. */
+/*@}*/
+
+/*! \name Interrupt Registers */
+/*@{*/
+#define EMAC_ISR_OFF                0x00000024  /*!< \brief Status register offset. */
+#define EMAC_ISR    (EMAC_BASE + EMAC_ISR_OFF)  /*!< \brief Status register address. */
+#define EMAC_IER_OFF                0x00000028  /*!< \brief Enable register offset. */
+#define EMAC_IER    (EMAC_BASE + EMAC_IER_OFF)  /*!< \brief Enable register address. */
+#define EMAC_IDR_OFF                0x0000002C  /*!< \brief Disable register offset. */
+#define EMAC_IDR    (EMAC_BASE + EMAC_IDR_OFF)  /*!< \brief Disable register address. */
+#define EMAC_IMR_OFF                0x00000030  /*!< \brief Mask register offset. */
+#define EMAC_IMR    (EMAC_BASE + EMAC_IMR_OFF)  /*!< \brief Mask register address. */
+
+#define EMAC_MFD                    0x00000001  /*!< \brief Management frame done. */
+#define EMAC_RCOMP                  0x00000002  /*!< \brief Receive complete. */
+#define EMAC_RXUBR                  0x00000004  /*!< \brief Receive used bit read. */
+#define EMAC_TXUBR                  0x00000008  /*!< \brief Transmit used bit read. */
+#define EMAC_TUND                   0x00000010  /*!< \brief Ethernet transmit buffer underrun. */
+#define EMAC_RLEX                   0x00000020  /*!< \brief Retry limit exceeded. */
+#define EMAC_TXERR                  0x00000040  /*!< \brief Transmit error. */
+#define EMAC_TCOMP                  0x00000080  /*!< \brief Transmit complete. */
+#define EMAC_LINK                   0x00000200  /*!< \brief . */
+#define EMAC_ROVR                   0x00000400  /*!< \brief Receive overrun. */
+#define EMAC_HRESP                  0x00000800  /*!< \brief DMA bus error. */
+#define EMAC_PFR                    0x00001000  /*!< \brief Pause frame received. */
+#define EMAC_PTZ                    0x00002000  /*!< \brief Pause time zero. */
+/*@}*/
+
+/*! \name PHY Maintenance Register */
+/*@{*/
+#define EMAC_MAN_OFF                0x00000034  /*!< \brief PHY maintenance register offset. */
+#define EMAC_MAN    (EMAC_BASE + EMAC_MAN_OFF)  /*!< \brief PHY maintenance register address. */
+
+#define EMAC_DATA                   0x0000FFFF  /*!< \brief PHY data mask. */
+#define EMAC_DATA_LSB                       0   /*!< \brief PHY data LSB. */
+#define EMAC_CODE                   0x00020000  /*!< \brief Fixed value. */
+#define EMAC_REGA                   0x007C0000  /*!< \brief PHY register address mask. */
+#define EMAC_REGA_LSB                       18  /*!< \brief PHY register address LSB. */
+#define EMAC_PHYA                   0x0F800000  /*!< \brief PHY address mask. */
+#define EMAC_PHYA_LSB                       23  /*!< \brief PHY address LSB. */
+#define EMAC_RW                     0x30000000  /*!< \brief PHY read/write command mask. */
+#define EMAC_RW_READ                0x20000000  /*!< \brief PHY read command. */
+#define EMAC_RW_WRITE               0x10000000  /*!< \brief PHY write command. */
+#define EMAC_SOF                    0x40000000  /*!< \brief Fixed value. */
+/*@}*/
+
+/*! \name Pause Time Register */
+/*@{*/
+#define EMAC_PTR_OFF                0x00000038  /*!< \brief Pause time register offset. */
+#define EMAC_PTR    (EMAC_BASE + EMAC_PTR_OFF)  /*!< \brief Pause time register address. */
+
+#define EMAC_PTIME                  0x0000FFFF  /*!< \brief Pause time mask. */
+/*@}*/
+
+/*! \name Statistics Registers */
+/*@{*/
+#define EMAC_PFRR_OFF               0x0000003C  /*!< \brief Pause frames received register offset. */
+#define EMAC_PFRR  (EMAC_BASE + EMAC_PFRR_OFF)  /*!< \brief Pause frames received register address. */
+#define EMAC_FTO_OFF                0x00000040  /*!< \brief Frames transmitted OK register offset. */
+#define EMAC_FTO    (EMAC_BASE + EMAC_FTO_OFF)  /*!< \brief Frames transmitted OK register address. */
+#define EMAC_SCF_OFF                0x00000044  /*!< \brief Single collision frame register offset. */
+#define EMAC_SCF    (EMAC_BASE + EMAC_SCF_OFF)  /*!< \brief Single collision frame register address. */
+#define EMAC_MCF_OFF                0x00000048  /*!< \brief Multiple collision frame register offset. */
+#define EMAC_MCF    (EMAC_BASE + EMAC_MCF_OFF)  /*!< \brief Multiple collision frame register address. */
+#define EMAC_FRO_OFF                0x0000004C  /*!< \brief Frames received OK register offset. */
+#define EMAC_FRO    (EMAC_BASE + EMAC_FRO_OFF)  /*!< \brief Frames received OK register address. */
+#define EMAC_FCSE_OFF               0x00000050  /*!< \brief Frame check sequence error register offset. */
+#define EMAC_FCSE   (EMAC_BASE + EMAC_FCSE_OFF) /*!< \brief Frame check sequence error register address. */
+#define EMAC_ALE_OFF                0x00000054  /*!< \brief Alignment error register offset. */
+#define EMAC_ALE    (EMAC_BASE + EMAC_ALE_OFF)  /*!< \brief Alignment error register address. */
+#define EMAC_DTF_OFF                0x00000058  /*!< \brief Deferred transmission frame register offset. */
+#define EMAC_DTF    (EMAC_BASE + EMAC_DTF_OFF)  /*!< \brief Deferred transmission frame register address. */
+#define EMAC_LCOL_OFF               0x0000005C  /*!< \brief Late collision register offset. */
+#define EMAC_LCOL   (EMAC_BASE + EMAC_LCOL_OFF) /*!< \brief Late collision register address. */
+#define EMAC_ECOL_OFF               0x00000060  /*!< \brief Excessive collision register offset. */
+#define EMAC_ECOL   (EMAC_BASE + EMAC_ECOL_OFF) /*!< \brief Excessive collision register address. */
+#define EMAC_TUNDR_OFF              0x00000064  /*!< \brief Transmit underrun error register offset. */
+#define EMAC_TUNDR (EMAC_BASE + EMAC_TUNDR_OFF) /*!< \brief Transmit underrun error register address. */
+#define EMAC_CSE_OFF                0x00000068  /*!< \brief Carrier sense error register offset. */
+#define EMAC_CSE    (EMAC_BASE + EMAC_CSE_OFF)  /*!< \brief Carrier sense error register address. */
+#define EMAC_RRE_OFF                0x0000006C  /*!< \brief Receive resource error register offset. */
+#define EMAC_RRE    (EMAC_BASE + EMAC_RRE_OFF)  /*!< \brief Receive resource error register address. */
+#define EMAC_ROV_OFF                0x00000070  /*!< \brief Receive overrun errors register offset. */
+#define EMAC_ROV    (EMAC_BASE + EMAC_ROV_OFF)  /*!< \brief Receive overrun errors register address. */
+#define EMAC_RSE_OFF                0x00000074  /*!< \brief Receive symbol errors register offset. */
+#define EMAC_RSE    (EMAC_BASE + EMAC_RSE_OFF)  /*!< \brief Receive symbol errors register address. */
+#define EMAC_ELE_OFF                0x00000078  /*!< \brief Excessive length errors register offset. */
+#define EMAC_ELE    (EMAC_BASE + EMAC_ELE_OFF)  /*!< \brief Excessive length errors register address. */
+#define EMAC_RJA_OFF                0x0000007C  /*!< \brief Receive jabbers register offset. */
+#define EMAC_RJA    (EMAC_BASE + EMAC_RJA_OFF)  /*!< \brief Receive jabbers register address. */
+#define EMAC_USF_OFF                0x00000080  /*!< \brief Undersize frames register offset. */
+#define EMAC_USF    (EMAC_BASE + EMAC_USF_OFF)  /*!< \brief Undersize frames register address. */
+#define EMAC_STE_OFF                0x00000084  /*!< \brief SQE test error register offset. */
+#define EMAC_STE    (EMAC_BASE + EMAC_STE_OFF)  /*!< \brief SQE test error register address. */
+#define EMAC_RLE_OFF                0x00000088  /*!< \brief Receive length field mismatch register offset. */
+#define EMAC_RLE    (EMAC_BASE + EMAC_RLE_OFF)  /*!< \brief Receive length field mismatch register address. */
+#define EMAC_TPF_OFF                0x0000008C  /*!< \brief Transmitted pause frames register offset. */
+#define EMAC_TPF    (EMAC_BASE + EMAC_TPF_OFF)  /*!< \brief Transmitted pause frames register address. */
+/*@}*/
+
+/*! \name MAC Adressing Registers */
+/*@{*/
+#define EMAC_HRB_OFF                0x00000090  /*!< \brief Hash address bottom[31:0]. */
+#define EMAC_HRB    (EMAC_BASE + EMAC_HRB_OFF)  /*!< \brief Hash address bottom[31:0]. */
+#define EMAC_HRT_OFF                0x00000094  /*!< \brief Hash address top[63:32]. */
+#define EMAC_HRT    (EMAC_BASE + EMAC_HRT_OFF)  /*!< \brief Hash address top[63:32]. */
+#define EMAC_SA1L_OFF               0x00000098  /*!< \brief Specific address 1 bottom, first 4 bytes. */
+#define EMAC_SA1L   (EMAC_BASE + EMAC_SA1L_OFF) /*!< \brief Specific address 1 bottom, first 4 bytes. */
+#define EMAC_SA1H_OFF               0x0000009C  /*!< \brief Specific address 1 top, last 2 bytes. */
+#define EMAC_SA1H   (EMAC_BASE + EMAC_SA1H_OFF) /*!< \brief Specific address 1 top, last 2 bytes. */
+#define EMAC_SA2L_OFF               0x000000A0  /*!< \brief Specific address 2 bottom, first 4 bytes. */
+#define EMAC_SA2L   (EMAC_BASE + EMAC_SA2L_OFF) /*!< \brief Specific address 2 bottom, first 4 bytes. */
+#define EMAC_SA2H_OFF               0x000000A4  /*!< \brief Specific address 2 top, last 2 bytes. */
+#define EMAC_SA2H   (EMAC_BASE + EMAC_SA2H_OFF) /*!< \brief Specific address 2 top, last 2 bytes. */
+#define EMAC_SA3L_OFF               0x000000A8  /*!< \brief Specific address 3 bottom, first 4 bytes. */
+#define EMAC_SA3L   (EMAC_BASE + EMAC_SA3L_OFF) /*!< \brief Specific address 3 bottom, first 4 bytes. */
+#define EMAC_SA3H_OFF               0x000000AC  /*!< \brief Specific address 3 top, last 2 bytes. */
+#define EMAC_SA3H   (EMAC_BASE + EMAC_SA3H_OFF) /*!< \brief Specific address 3 top, last 2 bytes. */
+#define EMAC_SA4L_OFF               0x000000B0  /*!< \brief Specific address 4 bottom, first 4 bytes. */
+#define EMAC_SA4L   (EMAC_BASE + EMAC_SA4L_OFF) /*!< \brief Specific address 4 bottom, first 4 bytes. */
+#define EMAC_SA4H_OFF               0x000000B4  /*!< \brief Specific address 4 top, last 2 bytes. */
+#define EMAC_SA4H   (EMAC_BASE + EMAC_SA4H_OFF) /*!< \brief Specific address 4 top, last 2 bytes. */
+/*@}*/
+
+/*! \name Type ID Register */
+/*@{*/
+#define EMAC_TID_OFF                0x000000B8  /*!< \brief Type ID checking register offset. */
+#define EMAC_TID    (EMAC_BASE + EMAC_TID_OFF)  /*!< \brief Type ID checking register address. */
+#define EMAC_TPQ_OFF                0x000000BC  /*!< \brief Transmit pause quantum register offset. */
+#define EMAC_TPQ    (EMAC_BASE + EMAC_TPQ_OFF)  /*!< \brief Transmit pause quantum register address. */
+/*@}*/
+
+/*! \name User Input/Output Register */
+/*@{*/
+#define EMAC_USRIO_OFF              0x000000C0  /*!< \brief User input/output register offset. */
+#define EMAC_USRIO (EMAC_BASE + EMAC_USRIO_OFF) /*!< \brief User input/output register address. */
+
+#define EMAC_RMII                   0x00000001  /*!< \brief Enable reduced MII. */
+#define EMAC_CLKEN                  0x00000002  /*!< \brief Enable tranceiver input clock. */
+/*@}*/
+
+/*! \name Wake On LAN Register */
+/*@{*/
+#define EMAC_WOL_OFF                0x000000C4  /*!< \brief Wake On LAN register offset. */
+#define EMAC_WOL    (EMAC_BASE + EMAC_WOL_OFF)  /*!< \brief Wake On LAN register address. */
+#define EMAC_IP                     0x0000FFFF  /*!< \brief ARP request IP address mask. */
+#define EMAC_MAG                    0x00010000  /*!< \brief Magic packet event enable. */
+#define EMAC_ARP                    0x00020000  /*!< \brief ARP request event enable. */
+#define EMAC_SA1                    0x00040000  /*!< \brief Specific address register 1 event enable. */
+/*@}*/
+
+/*! \name Revision Register */
+/*@{*/
+#define EMAC_REV_OFF                0x000000FC  /*!< \brief Revision register offset. */
+#define EMAC_REV    (EMAC_BASE + EMAC_REV_OFF)  /*!< \brief Revision register address. */
+#define EMAC_REVREF                 0x0000FFFF  /*!< \brief Revision. */
+#define EMAC_PARTREF                0xFFFF0000  /*!< \brief Part. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Emac */
+
+#endif                          /* _ARCH_ARM_AT91_EMAC_H_ */

include/arch/arm/at91_matrix.h

@@ -0,0 +1,83 @@
+#ifndef _ARCH_ARM_AT91_MATRIX_H_
+#define _ARCH_ARM_AT91_MATRIX_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_matrix.h
+ * \brief AT91 bus matrix user interface.
+ *
+ * \verbatim
+ *
+ * $Log: at91_matrix.h,v $
+ * Revision 1.1  2006/08/31 19:10:37  haraldkipp
+ * New peripheral register definitions for the AT91SAM9260.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Matrix
+ */
+/*@{*/
+
+/*! \name Master Configuration Registers */
+/*@{*/
+#define MATRIX_MCFG_OFF                 0x00000000      /*!< \brief Master configuration register offset. */
+#define MATRIX_MCFG(i)  (MATRIX_BASE + MATRIX_MCFG_OFF + (i) * 4)       /*!< \brief Master configuration register addresses. */
+/*@}*/
+
+/*! \name Slave Configuration Registers */
+/*@{*/
+#define MATRIX_SCFG_OFF                 0x00000040      /*!< \brief Slave configuration register offset. */
+#define MATRIX_SCFG(i)  (MATRIX_BASE + MATRIX_SCFG_OFF + (i) * 4)       /*!< \brief Slave configuration register addresses. */
+/*@}*/
+
+/*! \name Slave Priority Registers */
+/*@{*/
+#define MATRIX_PRAS_OFF                 0x00000080      /*!< \brief Slave priority register A offset. */
+#define MATRIX_PRAS(i)  (MATRIX_BASE + MATRIX_PRAS_OFF + (i) * 8)       /*!< \brief Slave priority register A addresses. */
+/*@}*/
+
+/*! \name Master Remap Control Register */
+/*@{*/
+#define MATRIX_MRCR_OFF                 0x00000100      /*!< \brief Remap control register offset. */
+#define MATRIX_MRCR (MATRIX_BASE + MATRIX_MRCR_OFF)     /*!< \brief Remap control register address. */
+#define MATRIX_MRCR_RCB0                0x00000001      /*!< \brief Enable remap for master 0. */
+#define MATRIX_MRCR_RCB1                0x00000002      /*!< \brief Enable remap for master 1. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Matrix */
+
+#endif                          /* _ARCH_ARM_AT91_MATRIX_H_ */

include/arch/arm/at91_mc.h

@@ -0,0 +1,135 @@
+#ifndef _ARCH_ARM_AT91_MC_H_
+#define _ARCH_ARM_AT91_MC_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_mc.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_mc.h,v $
+ * Revision 1.3  2006/07/26 11:21:35  haraldkipp
+ * Made it usable for assembler.
+ *
+ * Revision 1.2  2006/07/18 14:04:55  haraldkipp
+ * Base address removed. Should be specified in the upper level header.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+#define MC_RCR_OFF              0x00000000      /*!< \brief MC remap control register offset. */
+#define MC_RCR      (MC_BASE + MC_RCR_OFF)      /*!< \brief MC remap control register address. */
+#define MC_RCB                  0x00000001      /*!< \brief Remap command. */
+
+#define MC_ASR_OFF              0x00000004      /*!< \brief MC abort status register offset. */
+#define MC_ASR      (MC_BASE + MC_ASR_OFF)      /*!< \brief MC abort status register address. */
+#define MC_UNDADD               0x00000001      /*!< \brief Undefined Addess Abort status. */
+#define MC_MISADD               0x00000002      /*!< \brief Misaligned Addess Abort status. */
+#define MC_ABTSZ_MASK           0x00000300      /*!< \brief Abort size status mask. */
+#define MC_ABTSZ_BYTE           0x00000000      /*!< \brief Byte size abort. */
+#define MC_ABTSZ_HWORD          0x00000100      /*!< \brief Half-word size abort. */
+#define MC_ABTSZ_WORD           0x00000200      /*!< \brief Word size abort. */
+#define MC_ABTTYP_MASK          0x00000C00      /*!< \brief Abort type status mask. */
+#define MC_ABTTYP_DATAR         0x00000000      /*!< \brief Data read abort. */
+#define MC_ABTTYP_DATAW         0x00000400      /*!< \brief Data write abort. */
+#define MC_ABTTYP_FETCH         0x00000800      /*!< \brief Code fetch abort. */
+#define MC_MST_EMAC             0x00010000      /*!< \brief EMAC abort source. */
+#define MC_MST_PDC              0x00020000      /*!< \brief PDC abort source. */
+#define MC_MST_ARM              0x00040000      /*!< \brief ARM abort source. */
+#define MC_SVMST_EMAC           0x01000000      /*!< \brief Saved EMAC abort source. */
+#define MC_SVMST_PDC            0x02000000      /*!< \brief Saved PDC abort source. */
+#define MC_SVMST_ARM            0x04000000      /*!< \brief Saved ARM abort source. */
+
+#define MC_AASR_OFF             0x00000008      /*!< \brief MC abort address status register offset. */
+#define MC_AASR     (MC_BASE + MC_AASR_OFF)     /*!< \brief MC abort address status register address. */
+
+#define MC_FMR_OFF              0x00000060      /*!< \brief MC flash mode register offset. */
+#define MC_FMR      (MC_BASE + MC_FMR_OFF)      /*!< \brief MC flash mode register address. */
+#define MC_FRDY                 0x00000001      /*!< \brief Flash ready. */
+#define MC_LOCKE                0x00000004      /*!< \brief Lock error. */
+#define MC_PROGE                0x00000008      /*!< \brief Programming error. */
+#define MC_NEBP                 0x00000080      /*!< \brief No erase before programming. */
+#define MC_FWS_MASK             0x00000300      /*!< \brief Flash wait state mask. */
+#define MC_FWS_1R2W             0x00000000      /*!< \brief 1 cycle for read, 2 for write operations. */
+#define MC_FWS_2R3W             0x00000100      /*!< \brief 2 cycles for read, 3 for write operations. */
+#define MC_FWS_3R4W             0x00000200      /*!< \brief 3 cycles for read, 4 for write operations. */
+#define MC_FWS_4R4W             0x00000300      /*!< \brief 4 cycles for read and write operations. */
+#define MC_FMCN_MASK            0x00FF0000      /*!< \brief Flash microsecond cycle number mask. */
+
+#define MC_FCR_OFF              0x00000064      /*!< \brief MC flash command register offset. */
+#define MC_FCR      (MC_BASE + MC_FCR_OFF)      /*!< \brief MC flash command register address. */
+#define MC_FCMD_MASK            0x0000000F      /*!< \brief Flash command mask. */
+#define MC_FCMD_NOP             0x00000000      /*!< \brief No command. */
+#define MC_FCMD_WP              0x00000001      /*!< \brief Write page. */
+#define MC_FCMD_SLB             0x00000002      /*!< \brief Set lock bit. */
+#define MC_FCMD_WPL             0x00000003      /*!< \brief Write page and lock. */
+#define MC_FCMD_CLB             0x00000004      /*!< \brief Clear lock bit. */
+#define MC_FCMD_EA              0x00000008      /*!< \brief Erase all. */
+#define MC_FCMD_SGPB            0x0000000B      /*!< \brief Set general purpose NVM bit. */
+#define MC_FCMD_CGPB            0x0000000D      /*!< \brief Clear general purpose NVM bit. */
+#define MC_FCMD_SSB             0x0000000F      /*!< \brief Set security bit. */
+#define MC_PAGEN_MASK           0x0003FF00      /*!< \brief Page number mask. */
+#define MC_KEY                  0x5A000000      /*!< \brief Writing protect key. */
+
+#define MC_FSR_OFF              0x00000068      /*!< \brief MC flash status register offset. */
+#define MC_FSR      (MC_BASE + MC_FSR_OFF)      /*!< \brief MC flash status register address. */
+#define MC_SECURITY             0x00000010      /*!< \brief Security bit status. */
+
+#define MC_GPNVM0               0x00000100      /*!< \brief General purpose NVM bit 0. */
+#define MC_GPNVM1               0x00000200      /*!< \brief General purpose NVM bit 1. */
+#define MC_GPNVM2               0x00000400      /*!< \brief General purpose NVM bit 2. */
+
+#define MC_LOCKS0               0x00010000      /*!< \brief Lock region 0 lock status. */
+#define MC_LOCKS1               0x00020000      /*!< \brief Lock region 1 lock status. */
+#define MC_LOCKS2               0x00040000      /*!< \brief Lock region 2 lock status. */
+#define MC_LOCKS3               0x00080000      /*!< \brief Lock region 3 lock status. */
+#define MC_LOCKS4               0x00100000      /*!< \brief Lock region 4 lock status. */
+#define MC_LOCKS5               0x00200000      /*!< \brief Lock region 5 lock status. */
+#define MC_LOCKS6               0x00400000      /*!< \brief Lock region 6 lock status. */
+#define MC_LOCKS7               0x00800000      /*!< \brief Lock region 7 lock status. */
+#define MC_LOCKS8               0x01000000      /*!< \brief Lock region 8 lock status. */
+#define MC_LOCKS9               0x02000000      /*!< \brief Lock region 9 lock status. */
+#define MC_LOCKS10              0x04000000      /*!< \brief Lock region 10 lock status. */
+#define MC_LOCKS11              0x08000000      /*!< \brief Lock region 11 lock status. */
+#define MC_LOCKS12              0x10000000      /*!< \brief Lock region 12 lock status. */
+#define MC_LOCKS13              0x20000000      /*!< \brief Lock region 13 lock status. */
+#define MC_LOCKS14              0x40000000      /*!< \brief Lock region 14 lock status. */
+#define MC_LOCKS15              0x80000000      /*!< \brief Lock region 15 lock status. */
+
+#endif                          /* _ARCH_ARM_AT91_MC_H_ */

include/arch/arm/at91_mci.h

@@ -0,0 +1,276 @@
+#ifndef _ARCH_ARM_AT91_MCI_H_
+#define _ARCH_ARM_AT91_MCI_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_mci.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_mci.h,v $
+ * Revision 1.2  2006/09/05 12:32:13  haraldkipp
+ * Timeout multiplier settings renamed to follow Atmel's convention.
+ * 4-bit bus SDC setting corrected.
+ * Several comments added or corrected.
+ *
+ * Revision 1.1  2006/08/31 19:10:37  haraldkipp
+ * New peripheral register definitions for the AT91SAM9260.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Mci
+ */
+/*@{*/
+
+/*! \name MMC Control Register */
+/*@{*/
+#define MCI_CR_OFF              0x00000000      /*!< \brief Control register offset. */
+#define MCI_CR      (MCI_BASE + MCI_CR_OFF)     /*!< \brief Control register address. */
+#define MCI_MCIEN               0x00000001      /*!< \brief Interface enable. */
+#define MCI_MCIDIS              0x00000002      /*!< \brief Interface disable. */
+#define MCI_PWSEN               0x00000004      /*!< \brief Power save mode enable. */
+#define MCI_PWSDIS              0x00000008      /*!< \brief Power save mode disable. */
+#define MCI_SWRST               0x00000080      /*!< \brief Software reset. */
+/*@}*/
+
+/*! \name MMC Mode Register */
+/*@{*/
+#define MCI_MR_OFF              0x00000004      /*!< \brief Mode register offset. */
+#define MCI_MR      (MCI_BASE + MCI_MR_OFF)     /*!< \brief Mode register address. */
+#define MCI_CLKDIV              0x000000FF      /*!< \brief Clock divider mask. */
+#define MCI_CLKDIV_LSB                  0       /*!< \brief Clock divider LSB. */
+#define MCI_PWSDIV              0x00000700      /*!< \brief Power saving divider mask. */
+#define MCI_PWSDIV_LSB                  8       /*!< \brief Power saving divider LSB. */
+#define MCI_RDPROOF             0x00000800      /*!< \brief Enable read proof. */
+#define MCI_WRPROOF             0x00001000      /*!< \brief Enable write proof. */
+#define MCI_PDCFBYTE            0x00002000      /*!< \brief Force PDC byte transfer. */
+#define MCI_PDCPADV             0x00004000      /*!< \brief PDC padding value. */
+#define MCI_PDCMODE             0x00008000      /*!< \brief PDC-oriented mode. */
+#define MCI_BLKLEN              0xFFFF0000      /*!< \brief Data block length mask. */
+#define MCI_BLKLEN_LSB                  16      /*!< \brief Data block length LSB. */
+/*@}*/
+
+/*! \name MMC Data Timeout Register */
+/*@{*/
+#define MCI_DTOR_OFF            0x00000008      /*!< \brief Data timeout register offset. */
+#define MCI_DTOR    (MCI_BASE + MCI_DTOR_OFF)   /*!< \brief Data timeout register address. */
+#define MCI_DTOCYC              0x0000000F      /*!< \brief Data timeout cycle number mask. */
+#define MCI_DTOCYC_LSB                  0       /*!< \brief Data timeout cycle number LSB. */
+#define MCI_DTOMUL              0x00000070      /*!< \brief Data timeout multiplier mask. */
+#define MCI_DTOMUL_1            0x00000000      /*!< \brief Data timeout multiplier 1. */
+#define MCI_DTOMUL_16           0x00000010      /*!< \brief Data timeout multiplier 16. */
+#define MCI_DTOMUL_128          0x00000020      /*!< \brief Data timeout multiplier 128. */
+#define MCI_DTOMUL_256          0x00000030      /*!< \brief Data timeout multiplier 256. */
+#define MCI_DTOMUL_1K           0x00000040      /*!< \brief Data timeout multiplier 1024. */
+#define MCI_DTOMUL_4K           0x00000050      /*!< \brief Data timeout multiplier 4096. */
+#define MCI_DTOMUL_64K          0x00000060      /*!< \brief Data timeout multiplier 65536. */
+#define MCI_DTOMUL_1M           0x00000070      /*!< \brief Data timeout multiplier 1048576. */
+/*@}*/
+
+/*! \name MMC SDCard/SDIO Register */
+/*@{*/
+#define MCI_SDCR_OFF            0x0000000C      /*!< \brief SDC/SDIO register offset. */
+#define MCI_SDCR    (MCI_BASE + MCI_SDCR_OFF)   /*!< \brief SDC/SDIO register address. */
+#define MCI_SDCSEL              0x00000003      /*!< \brief SDC/SDIO slot mask. */
+#define MCI_SDCSEL_SLOTA        0x00000000      /*!< \brief Slot A selected. */
+#define MCI_SDCSEL_SLOTB        0x00000001      /*!< \brief Slot B selected. */
+#define MCI_SDCBUS              0x00000080      /*!< \brief SDC/SDIO 4-bit bus. */
+/*@}*/
+
+/*! \name MMC Argument Register */
+/*@{*/
+#define MCI_ARGR_OFF            0x00000010      /*!< \brief Argument register offset. */
+#define MCI_ARGR    (MCI_BASE + MCI_ARGR_OFF)   /*!< \brief Argument register address. */
+/*@}*/
+
+/*! \name MMC Command Register */
+/*@{*/
+#define MCI_CMDR_OFF            0x00000014      /*!< \brief Command register offset. */
+#define MCI_CMDR    (MCI_BASE + MCI_CMDR_OFF)   /*!< \brief Command register address. */
+#define MCI_CMDNB               0x0000003F      /*!< \brief Command number mask. */
+#define MCI_CMDNB_LSB                   0       /*!< \brief Command number LSB. */
+#define MCI_RSPTYP              0x000000C0      /*!< \brief Response type mask. */
+#define MCI_RSPTYP_NONE         0x00000000      /*!< \brief No response. */
+#define MCI_RSPTYP_48           0x00000040      /*!< \brief 48-bit response. */
+#define MCI_RSPTYP_136          0x00000080      /*!< \brief 136-bit response. */
+#define MCI_SPCMD               0x00000700      /*!< \brief Special command mask. */
+#define MCI_SPCMD_NONE          0x00000000      /*!< \brief Not a special command. */
+#define MCI_SPCMD_INIT          0x00000100      /*!< \brief Initialization command. */
+#define MCI_SPCMD_SYNC          0x00000200      /*!< \brief Synchronized command. */
+#define MCI_SPCMD_ICMD          0x00000400      /*!< \brief Interrupt command. */
+#define MCI_SPCMD_IRSP          0x00000500      /*!< \brief Interrupt response. */
+#define MCI_OPCMD               0x00000800      /*!< \brief Open drain command. */
+#define MCI_MAXLAT              0x00001000      /*!< \brief Maximum latency for command to response. */
+#define MCI_TRCMD               0x00030000      /*!< \brief Transfer command mask. */
+#define MCI_TRCMD_NONE          0x00000000      /*!< \brief No data transfer. */
+#define MCI_TRCMD_START         0x00010000      /*!< \brief Start data transfer. */
+#define MCI_TRCMD_STOP          0x00020000      /*!< \brief Stop data transfer. */
+#define MCI_TRDIR               0x00040000      /*!< \brief Read transfer. */
+#define MCI_TRTYP               0x00380000      /*!< \brief Transfer type mask. */
+#define MCI_TRTYP_MMC_SBLK      0x00000000      /*!< \brief MMC/SDC single block transfer. */
+#define MCI_TRTYP_MMC_MBLK      0x00080000      /*!< \brief MMC/SDC multiple block transfer. */
+#define MCI_TRTYP_MMC_STREAM    0x00100000      /*!< \brief MMC stream transfer. */
+#define MCI_TRTYP_SDIO_BYTE     0x00200000      /*!< \brief SDIO byte transfer. */
+#define MCI_TRTYP_SDIO_BLK      0x00280000      /*!< \brief SDIO block transfer. */
+#define MCI_IOSPCMD             0x03000000      /*!< \brief Specila SDIO command mask. */
+#define MCI_IOSPCMD_NONE        0x00000000      /*!< \brief Not a special SDIO command. */
+#define MCI_IOSPCMD_SUSPEND     0x01000000      /*!< \brief SDIO suspend command. */
+#define MCI_IOSPCMD_RESUME      0x02000000      /*!< \brief SDIO resume command. */
+/*@}*/
+
+/*! \name MMC Block Register */
+/*@{*/
+#define MCI_BLKR_OFF            0x00000018      /*!< \brief Block register offset. */
+#define MCI_BLKR    (MCI_BASE + MCI_BLKR_OFF)   /*!< \brief Block register address. */
+#define MCI_BCNT                0x0000FFFF      /*!< \brief MMC/SDIO block count or SDIO byte count mask. */
+#define MCI_BCNT_LSB                    0       /*!< \brief MMC/SDIO block count or SDIO byte count LSB. */
+/*@}*/
+
+/*! \name MMC Response Register */
+/*@{*/
+#define MCI_RSPR_OFF            0x00000020      /*!< \brief Response register offset. */
+#define MCI_RSPR    (MCI_BASE + MCI_RSPR_OFF)   /*!< \brief Response register address. */
+/*@}*/
+
+/*! \name MMC Receive Data Register */
+/*@{*/
+#define MCI_RDR_OFF             0x00000030      /*!< \brief Receive data register offset. */
+#define MCI_RDR     (MCI_BASE + MCI_RDR_OFF)    /*!< \brief Receive data register address. */
+/*@}*/
+
+/*! \name MMC Transmit Data Register */
+/*@{*/
+#define MCI_TDR_OFF             0x00000034      /*!< \brief Transmit data register offset. */
+#define MCI_TDR     (MCI_BASE + MCI_TDR_OFF)    /*!< \brief Transmit data register address. */
+/*@}*/
+
+/*! \name MMC Interrupt and Status Registers */
+/*@{*/
+#define MCI_SR_OFF              0x00000040      /*!< \brief Status register offset. */
+#define MCI_SR      (MCI_BASE + MCI_SR_OFF)     /*!< \brief Status register address. */
+
+#define MCI_IER_OFF             0x00000044      /*!< \brief Enable register offset. */
+#define MCI_IER     (MCI_BASE + MCI_IER_OFF)    /*!< \brief Enable register address. */
+
+#define MCI_IDR_OFF             0x00000048      /*!< \brief Disable register offset. */
+#define MCI_IDR     (MCI_BASE + MCI_IDR_OFF)    /*!< \brief Disable register address. */
+
+#define MCI_IMR_OFF             0x0000004C      /*!< \brief Mask register offset. */
+#define MCI_IMR     (MCI_BASE + MCI_IMR_OFF)    /*!< \brief Mask register address. */
+
+#define MCI_CMDRDY              0x00000001      /*!< \brief Command ready. */
+#define MCI_RXRDY               0x00000002      /*!< \brief Receiver ready. */
+#define MCI_TXRDY               0x00000004      /*!< \brief Transmit ready. */
+#define MCI_BLKE                0x00000008      /*!< \brief Data block ended. */
+#define MCI_DTIP                0x00000010      /*!< \brief Data transfer in progress. */
+#define MCI_NOTBUSY             0x00000020      /*!< \brief MCI not busy. */
+#define MCI_ENDRX               0x00000040      /*!< \brief End of receive buffer. */
+#define MCI_ENDTX               0x00000080      /*!< \brief End of transmit buffer. */
+#define MCI_SDIOIRQA            0x00000100      /*!< \brief Undocumented. */
+#define MCI_SDIOIRQB            0x00000200      /*!< \brief Undocumented. */
+#define MCI_RXBUFF              0x00004000      /*!< \brief Receive buffer full. */
+#define MCI_TXBUFE              0x00008000      /*!< \brief Transmit buffer empty. */
+#define MCI_RINDE               0x00010000      /*!< \brief Response index error. */
+#define MCI_RDIRE               0x00020000      /*!< \brief Response direction error. */
+#define MCI_RCRCE               0x00040000      /*!< \brief Response CRC error. */
+#define MCI_RENDE               0x00080000      /*!< \brief Response end bit error. */
+#define MCI_RTOE                0x00100000      /*!< \brief Response timeout error. */
+#define MCI_DCRCE               0x00200000      /*!< \brief Data CRC error. */
+#define MCI_DTOE                0x00400000      /*!< \brief Date timeout error. */
+#define MCI_OVRE                0x40000000      /*!< \brief Overrun error. */
+#define MCI_UNRE                0x80000000      /*!< \brief Underrun error. */
+
+/*@}*/
+
+#if defined(MCI_HAS_PDC)
+
+/*! \name SSC Receive Pointer Register */
+/*@{*/
+#define MCI_RPR    (MCI_BASE + PERIPH_RPR_OFF)  /*!< \brief PDC receive pointer register address. */
+/*@}*/
+
+/*! \name SSC Receive Counter Register */
+/*@{*/
+#define MCI_RCR    (MCI_BASE + PERIPH_RCR_OFF)  /*!< \brief PDC receive counter register address. */
+/*@}*/
+
+/*! \name SSC Transmit Pointer Register */
+/*@{*/
+#define MCI_TPR    (MCI_BASE + PERIPH_TPR_OFF)  /*!< \brief PDC transmit pointer register address. */
+/*@}*/
+
+/*! \name SSC Transmit Counter Register */
+/*@{*/
+#define MCI_TCR    (MCI_BASE + PERIPH_TCR_OFF)  /*!< \brief PDC transmit counter register address. */
+/*@}*/
+
+/*! \name SSC Receive Next Pointer Register */
+/*@{*/
+#define MCI_RNPR   (MCI_BASE + PERIPH_RNPR_OFF) /*!< \brief PDC receive next pointer register address. */
+/*@}*/
+
+/*! \name SSC Receive Next Counter Register */
+/*@{*/
+#define MCI_RNCR   (MCI_BASE + PERIPH_RNCR_OFF) /*!< \brief PDC receive next counter register address. */
+/*@}*/
+
+/*! \name SSC Transmit Next Pointer Register */
+/*@{*/
+#define MCI_TNPR   (MCI_BASE + PERIPH_TNPR_OFF) /*!< \brief PDC transmit next pointer register address. */
+/*@}*/
+
+/*! \name SSC Transmit Next Counter Register */
+/*@{*/
+#define MCI_TNCR   (MCI_BASE + PERIPH_TNCR_OFF) /*!< \brief PDC transmit next counter register address. */
+/*@}*/
+
+/*! \name SSC Transfer Control Register */
+/*@{*/
+#define MCI_PTCR   (MCI_BASE + PERIPH_PTCR_OFF) /*!< \brief PDC transfer control register address. */
+/*@}*/
+
+/*! \name SSC Transfer Status Register */
+/*@{*/
+#define MCI_PTSR   (MCI_BASE + PERIPH_PTSR_OFF) /*!< \brief PDC transfer status register address. */
+/*@}*/
+
+#endif
+
+/*@} xgNutArchArmAt91Mci */
+
+#endif                          /* _ARCH_ARM_AT91_MCI_H_ */

include/arch/arm/at91_pio.h

@@ -0,0 +1,278 @@
+#ifndef _ARCH_ARM_AT91_PIO_H_
+#define _ARCH_ARM_AT91_PIO_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_pio.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_pio.h,v $
+ * Revision 1.3  2006/09/29 12:43:08  haraldkipp
+ * Register offsets added, which are quite useful for assembler programming.
+ * Added some special PIO features, which are available on the AT91SAM92xx
+ * series.
+ *
+ * Revision 1.2  2006/08/31 19:11:18  haraldkipp
+ * Added register definitions for PIOC.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Pio
+ */
+/*@{*/
+
+/*! \name PIO Register Offsets */
+/*@{*/
+#define PIO_PER_OFF     0x00000000  /*!< \brief PIO enable register offset. */
+#define PIO_PDR_OFF     0x00000004  /*!< \brief PIO disable register offset. */
+#define PIO_PSR_OFF     0x00000008  /*!< \brief PIO status register offset. */
+#define PIO_OER_OFF     0x00000010  /*!< \brief Output enable register offset. */
+#define PIO_ODR_OFF     0x00000014  /*!< \brief Output disable register offset. */
+#define PIO_OSR_OFF     0x00000018  /*!< \brief Output status register offset. */
+#define PIO_IFER_OFF    0x00000020  /*!< \brief Input filter enable register offset. */
+#define PIO_IFDR_OFF    0x00000024  /*!< \brief Input filter disable register offset. */
+#define PIO_IFSR_OFF    0x00000028  /*!< \brief Input filter status register offset. */
+#define PIO_SODR_OFF    0x00000030  /*!< \brief Set output data register offset. */
+#define PIO_CODR_OFF    0x00000034  /*!< \brief Clear output data register offset. */
+#define PIO_ODSR_OFF    0x00000038  /*!< \brief Output data status register offset. */
+#define PIO_PDSR_OFF    0x0000003C  /*!< \brief Pin data status register offset. */
+#define PIO_IER_OFF     0x00000040  /*!< \brief Interrupt enable register offset. */
+#define PIO_IDR_OFF     0x00000044  /*!< \brief Interrupt disable register offset. */
+#define PIO_IMR_OFF     0x00000048  /*!< \brief Interrupt mask register offset. */
+#define PIO_ISR_OFF     0x0000004C  /*!< \brief Interrupt status register offset. */
+#if defined(PIO_HAS_MULTIDRIVER)
+#define PIO_MDER_OFF    0x00000050  /*!< \brief Multi-driver enable register offset. */
+#define PIO_MDDR_OFF    0x00000054  /*!< \brief Multi-driver disable register offset. */
+#define PIO_MDSR_OFF    0x00000058  /*!< \brief Multi-driver status register offset. */
+#endif /* PIO_HAS_MULTIDRIVER */
+#if defined(PIO_HAS_PULLUP)
+#define PIO_PUDR_OFF    0x00000060  /*!< \brief Pull-up disable register offset. */
+#define PIO_PUER_OFF    0x00000064  /*!< \brief Pull-up enable register offset. */
+#define PIO_PUSR_OFF    0x00000068  /*!< \brief Pull-up status register offset. */
+#endif /* PIO_HAS_PULLUP */
+#if defined(PIO_HAS_PERIPHERALSELECT)
+#define PIO_ASR_OFF     0x00000070  /*!< \brief PIO peripheral A select register offset. */
+#define PIO_BSR_OFF     0x00000074  /*!< \brief PIO peripheral B select register offset. */
+#define PIO_ABSR_OFF    0x00000078  /*!< \brief PIO peripheral AB status register offset. */
+#endif /* PIO_HAS_PERIPHERALSELECT */
+#if defined(PIO_HAS_OUTPUTWRITEENABLE)
+#define PIO_OWER_OFF    0x000000A0  /*!< \brief PIO output write enable register offset. */
+#define PIO_OWDR_OFF    0x000000A4  /*!< \brief PIO output write disable register offset. */
+#define PIO_OWSR_OFF    0x000000A8  /*!< \brief PIO output write status register offset. */
+#endif /* PIO_HAS_OUTPUTWRITEENABLE */
+/*@}*/
+
+/*! \name Single PIO Register Addresses */
+/*@{*/
+#if defined(PIO_BASE)
+#define PIO_PER     (PIO_BASE + PIO_PER_OFF)    /*!< \brief PIO enable register address. */
+#define PIO_PDR     (PIO_BASE + PIO_PDR_OFF)    /*!< \brief PIO disable register address. */
+#define PIO_PSR     (PIO_BASE + PIO_PSR_OFF)    /*!< \brief PIO status register address. */
+#define PIO_OER     (PIO_BASE + PIO_OER_OFF)    /*!< \brief Output enable register address. */
+#define PIO_ODR     (PIO_BASE + PIO_ODR_OFF)    /*!< \brief Output disable register address. */
+#define PIO_OSR     (PIO_BASE + PIO_OSR_OFF)    /*!< \brief Output status register address. */
+#define PIO_IFER    (PIO_BASE + PIO_IFER_OFF)   /*!< \brief Input filter enable register address. */
+#define PIO_IFDR    (PIO_BASE + PIO_IFDR_OFF)   /*!< \brief Input filter disable register address. */
+#define PIO_IFSR    (PIO_BASE + PIO_IFSR_OFF)   /*!< \brief Input filter status register address. */
+#define PIO_SODR    (PIO_BASE + PIO_SODR_OFF)   /*!< \brief Set output data register address. */
+#define PIO_CODR    (PIO_BASE + PIO_CODR_OFF)   /*!< \brief Clear output data register address. */
+#define PIO_ODSR    (PIO_BASE + PIO_ODSR_OFF)   /*!< \brief Output data status register address. */
+#define PIO_PDSR    (PIO_BASE + PIO_PDSR_OFF)   /*!< \brief Pin data status register address. */
+#define PIO_IER     (PIO_BASE + PIO_IER_OFF)    /*!< \brief Interrupt enable register address. */
+#define PIO_IDR     (PIO_BASE + PIO_IDR_OFF)    /*!< \brief Interrupt disable register address. */
+#define PIO_IMR     (PIO_BASE + PIO_IMR_OFF)    /*!< \brief Interrupt mask register address. */
+#define PIO_ISR     (PIO_BASE + PIO_ISR_OFF)    /*!< \brief Interrupt status register address. */
+#if defined(PIO_HAS_MULTIDRIVER)
+#define PIO_MDER    (PIO_BASE + PIO_MDER_OFF)   /*!< \brief Multi-driver enable register address. */
+#define PIO_MDDR    (PIO_BASE + PIO_MDDR_OFF)   /*!< \brief Multi-driver disable register address. */
+#define PIO_MDSR    (PIO_BASE + PIO_MDSR_OFF)   /*!< \brief Multi-driver status register address. */
+#endif /* PIO_HAS_MULTIDRIVER */
+#if defined(PIO_HAS_PULLUP)
+#define PIO_PUDR    (PIO_BASE + PIO_PUDR_OFF)   /*!< \brief Pull-up disable register address. */
+#define PIO_PUER    (PIO_BASE + PIO_PUER_OFF)   /*!< \brief Pull-up enable register address. */
+#define PIO_PUSR    (PIO_BASE + PIO_PUSR_OFF)   /*!< \brief Pull-up status register address. */
+#endif /* PIO_HAS_PULLUP */
+#if defined(PIO_HAS_PERIPHERALSELECT)
+#define PIO_ASR     (PIO_BASE + PIO_ASR_OFF)    /*!< \brief PIO peripheral A select register address. */
+#define PIO_BSR     (PIO_BASE + PIO_BSR_OFF)    /*!< \brief PIO peripheral B select register address. */
+#define PIO_ABSR    (PIO_BASE + PIO_ABSR_OFF)   /*!< \brief PIO peripheral AB status register address. */
+#endif /* PIO_HAS_PERIPHERALSELECT */
+#if defined(PIO_HAS_OUTPUTWRITEENABLE)
+#define PIO_OWER    (PIO_BASE + PIO_OWER_OFF)   /*!< \brief PIO output write enable register address. */
+#define PIO_OWDR    (PIO_BASE + PIO_OWDR_OFF)   /*!< \brief PIO output write disable register address. */
+#define PIO_OWSR    (PIO_BASE + PIO_OWSR_OFF)   /*!< \brief PIO output write status register address. */
+#endif /* PIO_HAS_OUTPUTWRITEENABLE */
+#endif /* PIO_BASE */
+/*@}*/
+
+/*! \name PIO A Register Addresses */
+/*@{*/
+#if defined(PIOA_BASE)
+#define PIOA_PER    (PIOA_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
+#define PIOA_PDR    (PIOA_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
+#define PIOA_PSR    (PIOA_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
+#define PIOA_OER    (PIOA_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
+#define PIOA_ODR    (PIOA_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
+#define PIOA_OSR    (PIOA_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
+#define PIOA_IFER   (PIOA_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
+#define PIOA_IFDR   (PIOA_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
+#define PIOA_IFSR   (PIOA_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
+#define PIOA_SODR   (PIOA_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
+#define PIOA_CODR   (PIOA_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
+#define PIOA_ODSR   (PIOA_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
+#define PIOA_PDSR   (PIOA_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
+#define PIOA_IER    (PIOA_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
+#define PIOA_IDR    (PIOA_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
+#define PIOA_IMR    (PIOA_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
+#define PIOA_ISR    (PIOA_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
+#if defined(PIO_HAS_MULTIDRIVER)
+#define PIOA_MDER   (PIOA_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
+#define PIOA_MDDR   (PIOA_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
+#define PIOA_MDSR   (PIOA_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
+#endif /* PIO_HAS_MULTIDRIVER */
+#if defined(PIO_HAS_PULLUP)
+#define PIOA_PUDR   (PIOA_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
+#define PIOA_PUER   (PIOA_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
+#define PIOA_PUSR   (PIOA_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
+#endif /* PIO_HAS_PULLUP */
+#if defined(PIO_HAS_PERIPHERALSELECT)
+#define PIOA_ASR    (PIOA_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
+#define PIOA_BSR    (PIOA_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
+#define PIOA_ABSR   (PIOA_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
+#endif /* PIO_HAS_PERIPHERALSELECT */
+#if defined(PIO_HAS_OUTPUTWRITEENABLE)
+#define PIOA_OWER   (PIOA_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
+#define PIOA_OWDR   (PIOA_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
+#define PIOA_OWSR   (PIOA_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
+#endif /* PIO_HAS_OUTPUTWRITEENABLE */
+#endif /* PIOA_BASE */
+/*@}*/
+
+/*! \name PIO B Register Addresses */
+/*@{*/
+#if defined(PIOB_BASE)
+#define PIOB_PER    (PIOB_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
+#define PIOB_PDR    (PIOB_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
+#define PIOB_PSR    (PIOB_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
+#define PIOB_OER    (PIOB_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
+#define PIOB_ODR    (PIOB_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
+#define PIOB_OSR    (PIOB_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
+#define PIOB_IFER   (PIOB_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
+#define PIOB_IFDR   (PIOB_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
+#define PIOB_IFSR   (PIOB_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
+#define PIOB_SODR   (PIOB_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
+#define PIOB_CODR   (PIOB_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
+#define PIOB_ODSR   (PIOB_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
+#define PIOB_PDSR   (PIOB_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
+#define PIOB_IER    (PIOB_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
+#define PIOB_IDR    (PIOB_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
+#define PIOB_IMR    (PIOB_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
+#define PIOB_ISR    (PIOB_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
+#if defined(PIO_HAS_MULTIDRIVER)
+#define PIOB_MDER   (PIOB_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
+#define PIOB_MDDR   (PIOB_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
+#define PIOB_MDSR   (PIOB_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
+#endif /* PIO_HAS_MULTIDRIVER */
+#if defined(PIO_HAS_PULLUP)
+#define PIOB_PUDR   (PIOB_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
+#define PIOB_PUER   (PIOB_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
+#define PIOB_PUSR   (PIOB_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
+#endif /* PIO_HAS_PULLUP */
+#if defined(PIO_HAS_PERIPHERALSELECT)
+#define PIOB_ASR    (PIOB_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
+#define PIOB_BSR    (PIOB_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
+#define PIOB_ABSR   (PIOB_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
+#endif /* PIO_HAS_PERIPHERALSELECT */
+#if defined(PIO_HAS_OUTPUTWRITEENABLE)
+#define PIOB_OWER   (PIOB_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
+#define PIOB_OWDR   (PIOB_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
+#define PIOB_OWSR   (PIOB_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
+#endif /* PIO_HAS_OUTPUTWRITEENABLE */
+#endif /* PIOB_BASE */
+/*@}*/
+
+/*! \name PIO C Register Addresses */
+/*@{*/
+#if defined(PIOC_BASE)
+#define PIOC_PER    (PIOC_BASE + PIO_PER_OFF)   /*!< \brief PIO enable register address. */
+#define PIOC_PDR    (PIOC_BASE + PIO_PDR_OFF)   /*!< \brief PIO disable register address. */
+#define PIOC_PSR    (PIOC_BASE + PIO_PSR_OFF)   /*!< \brief PIO status register address. */
+#define PIOC_OER    (PIOC_BASE + PIO_OER_OFF)   /*!< \brief Output enable register address. */
+#define PIOC_ODR    (PIOC_BASE + PIO_ODR_OFF)   /*!< \brief Output disable register address. */
+#define PIOC_OSR    (PIOC_BASE + PIO_OSR_OFF)   /*!< \brief Output status register address. */
+#define PIOC_IFER   (PIOC_BASE + PIO_IFER_OFF)  /*!< \brief Input filter enable register address. */
+#define PIOC_IFDR   (PIOC_BASE + PIO_IFDR_OFF)  /*!< \brief Input filter disable register address. */
+#define PIOC_IFSR   (PIOC_BASE + PIO_IFSR_OFF)  /*!< \brief Input filter status register address. */
+#define PIOC_SODR   (PIOC_BASE + PIO_SODR_OFF)  /*!< \brief Set output data register address. */
+#define PIOC_CODR   (PIOC_BASE + PIO_CODR_OFF)  /*!< \brief Clear output data register address. */
+#define PIOC_ODSR   (PIOC_BASE + PIO_ODSR_OFF)  /*!< \brief Output data status register address. */
+#define PIOC_PDSR   (PIOC_BASE + PIO_PDSR_OFF)  /*!< \brief Pin data status register address. */
+#define PIOC_IER    (PIOC_BASE + PIO_IER_OFF)   /*!< \brief Interrupt enable register address. */
+#define PIOC_IDR    (PIOC_BASE + PIO_IDR_OFF)   /*!< \brief Interrupt disable register address. */
+#define PIOC_IMR    (PIOC_BASE + PIO_IMR_OFF)   /*!< \brief Interrupt mask register address. */
+#define PIOC_ISR    (PIOC_BASE + PIO_ISR_OFF)   /*!< \brief Interrupt status register address. */
+#if defined(PIO_HAS_MULTIDRIVER)
+#define PIOC_MDER   (PIOC_BASE + PIO_MDER_OFF)  /*!< \brief Multi-driver enable register address. */
+#define PIOC_MDDR   (PIOC_BASE + PIO_MDDR_OFF)  /*!< \brief Multi-driver disable register address. */
+#define PIOC_MDSR   (PIOC_BASE + PIO_MDSR_OFF)  /*!< \brief Multi-driver status register address. */
+#endif /* PIO_HAS_MULTIDRIVER */
+#if defined(PIO_HAS_PULLUP)
+#define PIOC_PUDR   (PIOC_BASE + PIO_PUDR_OFF)  /*!< \brief Pull-up disable register address. */
+#define PIOC_PUER   (PIOC_BASE + PIO_PUER_OFF)  /*!< \brief Pull-up enable register address. */
+#define PIOC_PUSR   (PIOC_BASE + PIO_PUSR_OFF)  /*!< \brief Pull-up status register address. */
+#endif /* PIO_HAS_PULLUP */
+#if defined(PIO_HAS_PERIPHERALSELECT)
+#define PIOC_ASR    (PIOC_BASE + PIO_ASR_OFF)   /*!< \brief PIO peripheral A select register address. */
+#define PIOC_BSR    (PIOC_BASE + PIO_BSR_OFF)   /*!< \brief PIO peripheral B select register address. */
+#define PIOC_ABSR   (PIOC_BASE + PIO_ABSR_OFF)  /*!< \brief PIO peripheral AB status register address. */
+#endif /* PIO_HAS_PERIPHERALSELECT */
+#if defined(PIO_HAS_OUTPUTWRITEENABLE)
+#define PIOC_OWER   (PIOC_BASE + PIO_OWER_OFF)  /*!< \brief PIO output write enable register address. */
+#define PIOC_OWDR   (PIOC_BASE + PIO_OWDR_OFF)  /*!< \brief PIO output write disable register address. */
+#define PIOC_OWSR   (PIOC_BASE + PIO_OWSR_OFF)  /*!< \brief PIO output write status register address. */
+#endif /* PIO_HAS_OUTPUTWRITEENABLE */
+#endif /* PIOC_BASE */
+/*@}*/
+
+/*@} xgNutArchArmAt91Pio */
+
+#endif                          /* _ARCH_ARM_AT91_PIO_H_ */

include/arch/arm/at91_pit.h

@@ -0,0 +1,86 @@
+#ifndef _ARCH_ARM_AT91_PIT_H_
+#define _ARCH_ARM_AT91_PIT_H_
+
+/*
+ * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_pit.h
+ * \brief AT91 periodic interval timer.
+ *
+ * \verbatim
+ *
+ * $Log: at91_pit.h,v $
+ * Revision 1.1  2007/02/15 16:14:39  haraldkipp
+ * Periodic interrupt timer can be used as a system clock.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Pit
+ */
+/*@{*/
+
+/*! \name Periodic Inverval Timer Mode Register */
+/*@{*/
+#define PIT_MR_OFF              0x00000000  /*!< \brief Mode register offset. */
+#define PIT_MR      (PIT_BASE + PIT_MR_OFF) /*!< \brief Mode register address. */
+#define PIT_PIV                 0x000FFFFF  /*!< \brief Periodic interval value mask. */
+#define PIT_PIV_LSB                     0   /*!< \brief Periodic interval value LSB. */
+#define PIT_PITEN               0x01000000  /*!< \brief Periodic interval timer enable. */
+#define PIT_PITIEN              0x02000000  /*!< \brief Periodic interval timer interrupt enable. */
+/*@}*/
+
+/*! \name Periodic Inverval Timer Status Register */
+/*@{*/
+#define PIT_SR_OFF              0x00000004  /*!< \brief Status register offset. */
+#define PIT_SR      (PIT_BASE + PIT_SR_OFF) /*!< \brief Status register address. */
+#define PIT_PITS                0x00000001  /*!< \brief Timer has reached PIT_PIV. */
+/*@}*/
+
+/*! \name Periodic Inverval Timer Value and Image Registers */
+/*@{*/
+#define PIT_PIVR_OFF            0x00000008  /*!< \brief Value register offset. */
+#define PIT_PIVR  (PIT_BASE + PIT_PIVR_OFF) /*!< \brief Value register address. */
+#define PIT_PIIR_OFF            0x0000000C  /*!< \brief Image register offset. */
+#define PIT_PIIR  (PIT_BASE + PIT_PIIR_OFF) /*!< \brief Image register address. */
+#define PIT_CPIV                0x000FFFFF  /*!< \brief Current periodic interval value mask. */
+#define PIT_CPIV_LSB                    0   /*!< \brief Current periodic interval value LSB. */
+#define PIT_PICNT               0xFFF00000  /*!< \brief Periodic interval counter mask. */
+#define PIT_PICNT_LSB                  20   /*!< \brief Periodic interval counter LSB. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Pit */
+
+#endif  /* _ARCH_ARM_AT91_PIT_H_ */

include/arch/arm/at91_pmc.h

@@ -0,0 +1,220 @@
+#ifndef _ARCH_ARM_AT91_PMC_H_
+#define _ARCH_ARM_AT91_PMC_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_pmc.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_pmc.h,v $
+ * Revision 1.6  2006/09/29 12:43:44  haraldkipp
+ * Excluded second PLL from SAM7X builds. Corrected USB divider names.
+ *
+ * Revision 1.5  2006/08/31 19:08:14  haraldkipp
+ * Defining register offsets simplifies assembly programming.
+ *
+ * Revision 1.4  2006/08/05 11:59:23  haraldkipp
+ * Wrong PMC register offsets fixed.
+ *
+ * Revision 1.3  2006/07/26 11:22:05  haraldkipp
+ * Added shift values for multi-bit parameters.
+ *
+ * Revision 1.2  2006/07/18 14:05:26  haraldkipp
+ * Changed coding style to follow existing headers.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Pmc
+ */
+/*@{*/
+
+/*! \name System Clock Enable, Disable and Status Register */
+/*@{*/
+#define PMC_SCER_OFF                0x00000000  /*!< \brief System clock enable register offset. */
+#define PMC_SCER    (PMC_BASE + PMC_SCER_OFF)   /*!< \brief System clock enable register address. */
+#define PMC_SCDR_OFF                0x00000004  /*!< \brief System clock disable register offset. */
+#define PMC_SCDR    (PMC_BASE + PMC_SCDR_OFF)   /*!< \brief System clock disable register address. */
+#define PMC_SCSR_OFF                0x00000008  /*!< \brief System clock status register offset. */
+#define PMC_SCSR    (PMC_BASE + PMC_SCSR_OFF)   /*!< \brief System clock status register address. */
+
+#define PMC_PCK                     0x00000001  /*!< \brief Processor clock. */
+#define PMC_UHP                     0x00000040  /*!< \brief USB host port clock. */
+#define PMC_UDP                     0x00000080  /*!< \brief USB device port clock. */
+#define PMC_PCK0                    0x00000100  /*!< \brief Programmable clock 0 output. */
+#define PMC_PCK1                    0x00000200  /*!< \brief Programmable clock 1 output. */
+#define PMC_PCK2                    0x00000400  /*!< \brief Programmable clock 2 output. */
+#define PMC_PCK3                    0x00000800  /*!< \brief Programmable clock 3 output. */
+/*@}*/
+
+/*! \name Peripheral Clock Enable, Disable and Status Register */
+/*@{*/
+#define PMC_PCER_OFF                0x00000010  /*!< \brief Peripheral clock enable register offset. */
+#define PMC_PCER    (PMC_BASE + PMC_PCER_OFF)   /*!< \brief Peripheral clock enable register address. */
+#define PMC_PCDR_OFF                0x00000014  /*!< \brief Peripheral clock disable register offset. */
+#define PMC_PCDR    (PMC_BASE + PMC_PCDR_OFF)   /*!< \brief Peripheral clock disable register address. */
+#define PMC_PCSR_OFF                0x00000018  /*!< \brief Peripheral clock status register offset. */
+#define PMC_PCSR    (PMC_BASE + PMC_PCSR_OFF)   /*!< \brief Peripheral clock status register address. */
+/*@}*/
+
+/*! \name Clock Generator Main Oscillator Register */
+/*@{*/
+#define CKGR_MOR_OFF                0x00000020  /*!< \brief Main oscillator register offset. */
+#define CKGR_MOR    (PMC_BASE + CKGR_MOR_OFF)   /*!< \brief Main oscillator register address. */
+
+#define CKGR_MOSCEN                 0x00000001  /*!< \brief Main oscillator enable. */
+#define CKGR_OSCBYPASS              0x00000002  /*!< \brief Main oscillator bypass. */
+#define CKGR_OSCOUNT                0x0000FF00  /*!< \brief Main oscillator start-up time mask. */
+#define CKGR_OSCOUNT_LSB                    8   /*!< \brief Main oscillator start-up time LSB. */
+/*@}*/
+
+/*! \name Clock Generator Main Clock Frequency Register */
+/*@{*/
+#define CKGR_MCFR_OFF               0x00000024  /*!< \brief Main clock frequency register offset. */
+#define CKGR_MCFR   (PMC_BASE + CKGR_MCFR_OFF)  /*!< \brief Main clock frequency register address. */
+
+#define CKGR_MAINF                  0x0000FFFF  /*!< \brief Main clock frequency mask mask. */
+#define CKGR_MAINF_OFF                      0   /*!< \brief Main clock frequency mask LSB. */
+#define CKGR_MAINRDY                0x00010000  /*!< \brief Main clock ready. */
+/*@}*/
+
+/*! \name PLL Registers */
+/*@{*/
+#if defined (MCU_AT91SAM9260)
+#define CKGR_PLLAR_OFF              0x00000028  /*!< \brief Clock generator PLL register offset. */
+#define CKGR_PLLAR  (PMC_BASE + CKGR_PLLAR_OFF) /*!< \brief Clock generator PLL register address. */
+#define CKGR_PLLBR_OFF              0x0000002C  /*!< \brief Clock generator PLL register offset. */
+#define CKGR_PLLBR  (PMC_BASE + CKGR_PLLBR_OFF) /*!< \brief Clock generator PLL register address. */
+#elif defined (MCU_AT91SAM7X256)
+#define CKGR_PLLR_OFF               0x0000002C  /*!< \brief Clock generator PLL register offset. */
+#define CKGR_PLLR   (PMC_BASE + CKGR_PLLR_OFF)  /*!< \brief Clock generator PLL register address. */
+#endif
+
+#define CKGR_DIV                    0x000000FF  /*!< \brief Divider. */
+#define CKGR_DIV_LSB                        0   /*!< \brief Least significant bit of the divider. */
+#define CKGR_DIV_0                  0x00000000  /*!< \brief Divider output is 0. */
+#define CKGR_DIV_BYPASS             0x00000001  /*!< \brief Divider is bypassed. */
+#define CKGR_PLLCOUNT               0x00003F00  /*!< \brief PLL counter mask. */
+#define CKGR_PLLCOUNT_LSB                   8   /*!< \brief PLL counter LSB. */
+#define CKGR_OUT                    0x0000C000  /*!< \brief PLL output frequency range. */
+#define CKGR_OUT_0                  0x00000000  /*!< \brief Please refer to the PLL datasheet. */
+#define CKGR_OUT_1                  0x00004000  /*!< \brief Please refer to the PLL datasheet. */
+#define CKGR_OUT_2                  0x00008000  /*!< \brief Please refer to the PLL datasheet. */
+#define CKGR_OUT_3                  0x0000C000  /*!< \brief Please refer to the PLL datasheet. */
+#define CKGR_MUL                    0x07FF0000  /*!< \brief PLL multiplier. */
+#define CKGR_MUL_LSB                        16  /*!< \brief Least significant bit of the PLL multiplier. */
+#define CKGR_USBDIV                 0x30000000  /*!< \brief Divider for USB clocks. */
+#define CKGR_USBDIV_1               0x00000000  /*!< \brief Divider output is PLL clock output. */
+#define CKGR_USBDIV_2               0x10000000  /*!< \brief Divider output is PLL clock output divided by 2. */
+#define CKGR_USBDIV_4               0x20000000  /*!< \brief Divider output is PLL clock output divided by 4. */
+/*@}*/
+
+/*! \name Master Clock Register */
+/*@{*/
+#define PMC_MCKR_OFF                0x00000030  /*!< \brief Master clock register offset. */
+#define PMC_MCKR    (PMC_BASE + PMC_MCKR_OFF)   /*!< \brief Master clock register address. */
+#define PMC_ACKR_OFF                0x00000034  /*!< \brief Application clock register offset. */
+#define PMC_ACKR    (PMC_BASE + PMC_ACKR_OFF)   /*!< \brief Application clock register address. */
+#define PMC_PCKR0_OFF               0x00000040  /*!< \brief Programmable clock 0 register offset. */
+#define PMC_PCKR0   (PMC_BASE + PMC_PCKR0_OFF)  /*!< \brief Programmable clock 0 register address. */
+#define PMC_PCKR1_OFF               0x00000044  /*!< \brief Programmable clock 1 register offset. */
+#define PMC_PCKR1   (PMC_BASE + PMC_PCKR1_OFF)  /*!< \brief Programmable clock 1 register address. */
+#define PMC_PCKR2_OFF               0x00000048  /*!< \brief Programmable clock 2 register offset. */
+#define PMC_PCKR2   (PMC_BASE + PMC_PCKR2_OFF)  /*!< \brief Programmable clock 2 register address. */
+#define PMC_PCKR3_OFF               0x0000004C  /*!< \brief Programmable clock 3 register offset. */
+#define PMC_PCKR3   (PMC_BASE + PMC_PCKR3_OFF)  /*!< \brief Programmable clock 3 register address. */
+
+#define PMC_CSS                     0x00000003  /*!< \brief Clock selection mask. */
+#define PMC_CSS_SLOW_CLK            0x00000000  /*!< \brief Slow clock selected. */
+#define PMC_CSS_MAIN_CLK            0x00000001  /*!< \brief Main clock selected. */
+#if defined (MCU_AT91SAM9260)
+#define PMC_CSS_PLLA_CLK            0x00000002  /*!< \brief PLL A clock selected. */
+#define PMC_CSS_PLLB_CLK            0x00000003  /*!< \brief PLL B clock selected. */
+#elif defined (MCU_AT91SAM7X256)
+#define PMC_CSS_PLL_CLK             0x00000003  /*!< \brief PLL clock selected. */
+#endif
+#define PMC_PRES                    0x0000001C  /*!< \brief Clock prescaler mask. */
+#define PMC_PRES_LSB                        2   /*!< \brief Clock prescaler LSB. */
+#define PMC_PRES_CLK                0x00000000  /*!< \brief Selected clock, not divided. */
+#define PMC_PRES_CLK_2              0x00000004  /*!< \brief Selected clock divided by 2. */
+#define PMC_PRES_CLK_4              0x00000008  /*!< \brief Selected clock divided by 4. */
+#define PMC_PRES_CLK_8              0x0000000C  /*!< \brief Selected clock divided by 8. */
+#define PMC_PRES_CLK_16             0x00000010  /*!< \brief Selected clock divided by 16. */
+#define PMC_PRES_CLK_32             0x00000014  /*!< \brief Selected clock divided by 32. */
+#define PMC_PRES_CLK_64             0x00000018  /*!< \brief Selected clock divided by 64. */
+#if defined (MCU_AT91SAM9260)
+#define PMC_MDIV                    0x00000300  /*!< \brief Master clock division mask. */
+#define PMC_MDIV_1                  0x00000000  /*!< \brief Processor clock, not divided. */
+#define PMC_MDIV_2                  0x00000100  /*!< \brief Processor clock divided by 2. */
+#define PMC_MDIV_4                  0x00000200  /*!< \brief Processor clock divided by 4. */
+#endif
+/*@}*/
+
+/*! \name Power Management Status and Interrupt Registers */
+/*@{*/
+#define PMC_IER_OFF                 0x00000060  /*!< \brief Interrupt enable register offset. */
+#define PMC_IER     (PMC_BASE + PMC_IER_OFF)    /*!< \brief Interrupt enable register address. */
+#define PMC_IDR_OFF                 0x00000064  /*!< \brief Interrupt disable register offset. */
+#define PMC_IDR     (PMC_BASE + PMC_IDR_OFF)    /*!< \brief Interrupt disable register address. */
+#define PMC_SR_OFF                  0x00000068  /*!< \brief Status register offset. */
+#define PMC_SR      (PMC_BASE + PMC_SR_OFF)     /*!< \brief Status register address. */
+#define PMC_IMR_OFF                 0x0000006C  /*!< \brief Interrupt mask register offset. */
+#define PMC_IMR     (PMC_BASE + PMC_IMR_OFF)    /*!< \brief Interrupt mask register address. */
+
+#define PMC_MOSCS                   0x00000001  /*!< \brief Main oscillator. */
+#if defined (MCU_AT91SAM9260)
+#define PMC_LOCKA                   0x00000002  /*!< \brief PLL A lock. */
+#define PMC_LOCKB                   0x00000004  /*!< \brief PLL B lock. */
+#elif defined (MCU_AT91SAM7X256)
+#define PMC_LOCK                    0x00000004  /*!< \brief PLL lock. */
+#endif
+#define PMC_MCKRDY                  0x00000008  /*!< \brief Master clock ready. */
+#define PMC_OSC_SEL                 0x00000080  /*!< \brief Slow clock oscillator selection. */
+#define PMC_PCKRDY0                 0x00000100  /*!< \brief Programmable clock 0 ready. */
+#define PMC_PCKRDY1                 0x00000200  /*!< \brief Programmable clock 1 ready. */
+#define PMC_PCKRDY2                 0x00000400  /*!< \brief Programmable clock 2 ready. */
+#define PMC_PCKRDY3                 0x00000800  /*!< \brief Programmable clock 3 ready. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Pmc */
+
+
+#endif                          /* _ARCH_ARM_AT91_PMC_H_ */

include/arch/arm/at91_ps.h

@@ -0,0 +1,80 @@
+#ifndef _ARCH_ARM_AT91_PS_H_
+#define _ARCH_ARM_AT91_PS_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_ps.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_ps.h,v $
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Ps
+ */
+/*@{*/
+
+/*!
+ * \name PS Control Register
+ */
+/*@{*/
+
+/*! \brief Register address.
+ *
+ * This register allows to stop the CPU clock. The clock is automatically
+ * enabled after reset and by any interrupt.
+ */
+#define PS_CR       (PS_BASE + 0x00)
+/*@}*/
+
+/*!
+ * \name Peripheral Clock Control Registers
+ */
+/*@{*/
+#define PS_PCER     (PS_BASE + 0x04)    /*!< \brief Peripheral clock enable register address. */
+#define PS_PCDR     (PS_BASE + 0x08)    /*!< \brief Peripheral clock disable register address. */
+#define PS_PCSR     (PS_BASE + 0x0C)    /*!< \brief Peripheral clock status register address. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Ps */
+
+#endif                          /* _ARCH_ARM_AT91_PS_H_ */
+

include/arch/arm/at91_rstc.h

@@ -0,0 +1,95 @@
+#ifndef _ARCH_ARM_AT91_RSTC_H_
+#define _ARCH_ARM_AT91_RSTC_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_rstc.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_rstc.h,v $
+ * Revision 1.2  2006/08/31 19:13:15  haraldkipp
+ * Wakeup bit and LSB of external reset length added.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Rstc
+ */
+/*@{*/
+
+/*! \name Reset Controller Control Register */
+/*@{*/
+#define RSTC_CR         (RSTC_BASE + 0x00)      /*!< \brief Reset controller control register address. */
+#define RSTC_PROCRST            0x00000001      /*!< \brief Processor reset. */
+#define RSTC_PERRST             0x00000004      /*!< \brief Peripheral reset. */
+#define RSTC_EXTRST             0x00000008      /*!< \brief External reset. */
+#define RSTC_KEY                0xA5000000      /*!< \brief Password. */
+/*@}*/
+
+/*! \name Reset Controller Status Register */
+/*@{*/
+#define RSTC_SR         (RSTC_BASE + 0x04)      /*!< \brief Reset controller status register address. */
+#define RSTC_URSTS              0x00000001      /*!< \brief User reset status. */
+#define RSTC_BODSTS             0x00000002      /*!< \brief Brownout detection status. */
+#define RSTC_RSTTYP             0x00000700      /*!< \brief Reset type. */
+#define RSTC_RSTTYP_POWERUP     0x00000000      /*!< \brief Power-up reset. */
+#define RSTC_RSTTYP_WAKEUP      0x00000100      /*!< \brief VDDCORE rising. */
+#define RSTC_RSTTYP_WATCHDOG    0x00000200      /*!< \brief Watchdog reset. */
+#define RSTC_RSTTYP_SOFTWARE    0x00000300      /*!< \brief Software reset. */
+#define RSTC_RSTTYP_USER        0x00000400      /*!< \brief User reset. */
+#define RSTC_RSTTYP_BROWNOUT    0x00000500      /*!< \brief Brownout reset. */
+#define RSTC_NRSTL              0x00010000      /*!< \brief NRST pin level. */
+#define RSTC_SRCMP              0x00020000      /*!< \brief Software reset command in progress. */
+/*@}*/
+
+/*! \name Reset Controller Mode Register */
+/*@{*/
+#define RSTC_MR         (RSTC_BASE + 0x08)      /*!< \brief Reset controller mode register address. */
+#define RSTC_URSTEN             0x00000001      /*!< \brief User reset enable. */
+#define RSTC_URSTIEN            0x00000010      /*!< \brief User reset interrupt enable. */
+#define RSTC_ERSTL              0x00000F00      /*!< \brief External reset length. */
+#define RSTC_ERSTL_LSB                  8       /*!< \brief Least significant bit of external reset length. */
+#define RSTC_BODIEN             0x00010000      /*!< \brief Brown-out detection interrupt enable. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Rstc */
+
+#endif                          /* _ARCH_ARM_AT91_RSTC_H_ */

include/arch/arm/at91_sdramc.h

@@ -0,0 +1,155 @@
+#ifndef _ARCH_ARM_AT91_SDRAMC_H_
+#define	_ARCH_ARM_AT91_SDRAMC_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_sdramc.h
+ * \brief AT91 SDRAM controller.
+ *
+ * \verbatim
+ *
+ * $Log: at91_sdramc.h,v $
+ * Revision 1.1  2006/08/31 19:10:38  haraldkipp
+ * New peripheral register definitions for the AT91SAM9260.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Sdramc
+ */
+/*@{*/
+
+/*! \name SDRAM Controller Mode Register */
+/*@{*/
+#define SDRAMC_MR_OFF                   0x00000000      /*!< \brief Mode register offset. */
+#define SDRAMC_MR   (SDRAMC_BASE + SDRAMC_MR_OFF)       /*!< \brief Mode register address. */
+#define SDRAMC_MODE                     0x00000007      /*!< \brief Command mode mask. */
+#define SDRAMC_MODE_NORMAL              0x00000000      /*!< \brief Normal mode. */
+#define SDRAMC_MODE_NOP                 0x00000001      /*!< \brief Issues a NOP command when accessed. */
+#define SDRAMC_MODE_PRCGALL             0x00000002      /*!< \brief Issues an "All Banks Precharge" command when accessed. */
+#define SDRAMC_MODE_LMR                 0x00000003      /*!< \brief Issues a "Load Mode Register" command when accessed. */
+#define SDRAMC_MODE_RFSH                0x00000004      /*!< \brief Issues a "Auto Refresh" command when accessed. */
+#define SDRAMC_MODE_EXT_LMR             0x00000005      /*!< \brief Issues a "Extended Load Mode Register" command when accessed. */
+#define SDRAMC_MODE_DEEP                0x00000006      /*!< \brief Enters deep power down mode. */
+/*@}*/
+
+/*! \name SDRAM Controller Refresh Timer Register */
+/*@{*/
+#define SDRAMC_TR_OFF                   0x00000004      /*!< \brief Refresh timer register offset. */
+#define SDRAMC_TR   (SDRAMC_BASE + SDRAMC_TR_OFF)       /*!< \brief Refresh timer register address. */
+#define SDRAMC_COUNT                    0x00000FFF      /*!< \brief Refresh timer count mask. */
+/*@}*/
+
+/*! \name SDRAM Controller Configuration Register */
+/*@{*/
+#define SDRAMC_CR_OFF                   0x00000008      /*!< \brief Configuration register offset. */
+#define SDRAMC_CR   (SDRAMC_BASE + SDRAMC_CR_OFF)       /*!< \brief Configuration register address. */
+#define SDRAMC_NC                       0x00000003      /*!< \brief Number of column bits. */
+#define SDRAMC_NC_8                     0x00000000      /*!< \brief 8 column bits. */
+#define SDRAMC_NC_9                     0x00000001      /*!< \brief 9 column bits. */
+#define SDRAMC_NC_10                    0x00000002      /*!< \brief 10 column bits. */
+#define SDRAMC_NC_11                    0x00000003      /*!< \brief 11 column bits. */
+#define SDRAMC_NR                       0x0000000C      /*!< \brief Number of row bits. */
+#define SDRAMC_NR_11                    0x00000000      /*!< \brief 11 row bits. */
+#define SDRAMC_NR_12                    0x00000004      /*!< \brief 12 row bits. */
+#define SDRAMC_NR_13                    0x00000008      /*!< \brief 13 row bits. */
+#define SDRAMC_NB                       0x00000010      /*!< \brief 4 banks. */
+#define SDRAMC_CAS                      0x00000060      /*!< \brief CAS latency. */
+#define SDRAMC_CAS_1                    0x00000020      /*!< \brief CAS latency of 1 cycle. */
+#define SDRAMC_CAS_2                    0x00000040      /*!< \brief CAS latency of 2 cycles. */
+#define SDRAMC_CAS_3                    0x00000060      /*!< \brief CAS latency of 3 cycles. */
+#define SDRAMC_DBW                      0x00000080      /*!< \brief 16-bit data bus. */
+#define SDRAMC_TWR                      0x00000F00      /*!< \brief Write recovery delay. */
+#define SDRAMC_TWR_LSB                          8       /*!< \brief Write recovery delay. */
+#define SDRAMC_TRC                      0x0000F000      /*!< \brief Row cycle delay. */
+#define SDRAMC_TRC_LSB                          12      /*!< \brief Row cycle delay. */
+#define SDRAMC_TRP                      0x000F0000      /*!< \brief Row precharge delay. */
+#define SDRAMC_TRP_LSB                          16      /*!< \brief Row precharge delay. */
+#define SDRAMC_TRCD                     0x00F00000      /*!< \brief Row to column delay. */
+#define SDRAMC_TRCD_LSB                         20      /*!< \brief Row to column delay. */
+#define SDRAMC_TRAS                     0x0F000000      /*!< \brief Active to precharge delay. */
+#define SDRAMC_TRAS_LSB                         24      /*!< \brief Active to precharge delay. */
+#define SDRAMC_TXSR                     0xF0000000      /*!< \brief Exit self refresh to active delay. */
+#define SDRAMC_TXSR_LSB                         28      /*!< \brief Exit self refresh to active delay. */
+/*@}*/
+
+/*! \name SDRAM Controller Low Power Register */
+/*@{*/
+#define SDRAMC_LPR_OFF                  0x00000010      /*!< \brief Low power register offset. */
+#define SDRAMC_LPR  (SDRAMC_BASE + SDRAMC_LPR_OFF)      /*!< \brief Low power register address. */
+#define SDRAMC_LPCB                     0x00000003      /*!< \brief Low power configuration mask. */
+#define SDRAMC_LPCB_DISABLE             0x00000000      /*!< \brief Low power feature disabled. */
+#define SDRAMC_LPCB_SELF_REFRESH        0x00000001      /*!< \brief Enable self refresh. */
+#define SDRAMC_LPCB_POWER_DOWN          0x00000002      /*!< \brief Issues a "Power Down" command when accessed.. */
+#define SDRAMC_LPCB_DEEP_POWER_DOWN     0x00000003      /*!< \brief Enters deep power down mode. */
+#define SDRAMC_PASR                     0x00000070      /*!< \brief Partial array self-refresh mask. */
+#define SDRAMC_PASR_LSB                         4       /*!< \brief Partial array self-refresh LSB. */
+#define SDRAMC_TCSR                     0x00000300      /*!< \brief Temperature compensated self-refresh mask. */
+#define SDRAMC_TCSR_LSB                         8       /*!< \brief Temperature compensated self-refresh LSB. */
+#define SDRAMC_DS                       0x00000C00      /*!< \brief Drive strength mask. */
+#define SDRAMC_DS_LSB                           10      /*!< \brief Drive strength LSB. */
+#define SDRAMC_TIMEOUT                  0x00003000      /*!< \brief Mask of time to define when low-power mode is enabled. */
+#define SDRAMC_TIMEOUT_0                0x00000000      /*!< \brief Activate immediately. */
+#define SDRAMC_TIMEOUT_64               0x00001000      /*!< \brief Activate after 64 clock cycles after the end of the last transfer. */
+#define SDRAMC_TIMEOUT_128              0x00002000      /*!< \brief Activate after 64 clock cycles after the end of the last transfer. */
+/*@}*/
+
+/*! \name SDRAM Controller Interrupt Registers */
+/*@{*/
+#define SDRAMC_IER_OFF                  0x00000014      /*!< \brief Interrupt enable register offset. */
+#define SDRAMC_IER  (SDRAMC_BASE + SDRAMC_IER_OFF)      /*!< \brief Interrupt enable register address. */
+#define SDRAMC_IDR_OFF                  0x00000018      /*!< \brief Interrupt disable register offset. */
+#define SDRAMC_IDR  (SDRAMC_BASE + SDRAMC_IDR_OFF)      /*!< \brief Interrupt disable register address. */
+#define SDRAMC_IMR_OFF                  0x0000001C      /*!< \brief Interrupt mask register offset. */
+#define SDRAMC_IMR  (SDRAMC_BASE + SDRAMC_IMR_OFF)      /*!< \brief Interrupt mask register address. */
+#define SDRAMC_ISR_OFF                  0x00000020      /*!< \brief Interrupt status register offset. */
+#define SDRAMC_ISR  (SDRAMC_BASE + SDRAMC_ISR_OFF)      /*!< \brief Interrupt status register address. */
+#define SDRAMC_RES                      0x00000001      /*!< \brief Refresh error status. */
+/*@}*/
+
+/*! \name SDRAM Controller Memory Device Register */
+/*@{*/
+#define SDRAMC_MDR_OFF                  0x00000024      /*!< \brief Memory device register offset. */
+#define SDRAMC_MDR  (SDRAMC_BASE + SDRAMC_MDR_OFF)      /*!< \brief Memory device register address. */
+#define SDRAMC_MD                       0x00000003      /*!< \brief Memory device type mask. */
+#define SDRAMC_MD                       0x00000003      /*!< \brief Memory device type mask. */
+#define SDRAMC_MD_SDRAM                 0x00000000      /*!< \brief SDRAM. */
+#define SDRAMC_MD_LPSDRAM               0x00000001      /*!< \brief Low power SDRAM. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Sdramc */
+
+#endif                          /* _ARCH_ARM_AT91_SDRAMC_H_ */

include/arch/arm/at91_sf.h

@@ -0,0 +1,115 @@
+#ifndef _ARCH_ARM_AT91_SF_H_
+#define _ARCH_ARM_AT91_SF_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_sf.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_sf.h,v $
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Sf
+ */
+/*@{*/
+
+/*! \name Chip Identification Registers */
+/*@{*/
+#define SF_CIDR         (SF_BASE + 0x00)        /*!< \brief Chip ID register address. */
+#define SF_EXID         (SF_BASE + 0x04)        /*!< \brief Chip ID extension register address. */
+#define SF_VERSION              0x0000001F      /*!< \brief Version number mask. */
+
+#define SF_NVPSIZ               0x00000F00      /*!< \brief Masks non-volatile program memory size. */
+#define SF_NVPSIZ_NONE          0x00000000      /*!< \brief No NV program memory. */
+#define SF_NVPSIZ_32K           0x00000300      /*!< \brief 32 kBytes NV program memory. */
+#define SF_NVPSIZ_64K           0x00000500      /*!< \brief 64 kBytes NV program memory. */
+#define SF_NVPSIZ_128K          0x00000700      /*!< \brief 128 kBytes NV program memory. */
+#define SF_NVPSIZ_256K          0x00000900      /*!< \brief 256 kBytes NV program memory. */
+
+#define SF_NVDSIZ               0x0000F000      /*!< \brief Masks non-volatile data memory size. */
+#define SF_NVDSIZ_NONE          0x00000000      /*!< \brief No NV data memory. */
+
+#define SF_VDSIZ                0x000F0000      /*!< \brief Masks volatile data memory size. */
+#define SF_VDSIZ_NONE           0x00000000      /*!< \brief No volatile data memory. */
+#define SF_VDSIZ_1K             0x00010000      /*!< \brief 1 kBytes volatile data memory. */
+#define SF_VDSIZ_2K             0x00020000      /*!< \brief 2 kBytes volatile data memory. */
+#define SF_VDSIZ_4K             0x00040000      /*!< \brief 4 kBytes volatile data memory. */
+#define SF_VDSIZ_8K             0x00080000      /*!< \brief 8 kBytes volatile data memory. */
+
+#define SF_ARCH                 0x0FF00000      /*!< \brief Architecture code mask. */
+#define SF_ARCH_AT91x40         0x04000000      /*!< \brief AT91x40 architecture. */
+#define SF_ARCH_AT91x55         0x05500000      /*!< \brief AT91x55 architecture. */
+#define SF_ARCH_AT91x63         0x06300000      /*!< \brief AT91x63 architecture. */
+
+#define SF_NVPTYP               0x70000000      /*!< \brief Masks non-volatile program memory type. */
+#define SF_NVPTYP_M             0x01000000      /*!< \brief M or F series. */
+#define SF_NVPTYP_C             0x02000000      /*!< \brief C series. */
+#define SF_NVPTYP_S             0x03000000      /*!< \brief S series. */
+#define SF_NVPTYP_R             0x04000000      /*!< \brief R series. */
+
+#define SF_EXT                  0x80000000      /*!< \brief Extension flag. */
+
+/*@}*/
+
+/*! \name Reset Status Flag Register */
+/*@{*/
+#define SF_RSR          (SF_BASE + 0x08)        /*!< \brief Reset status register address. */
+#define SF_EXT_RESET            0x0000006C      /*!< \brief Reset caused by external pin. */
+#define SF_WD_RESET             0x00000053      /*!< \brief Reset caused by internal watch dog. */
+/*@}*/
+
+/*! \name Memory Mode Register */
+/*@{*/
+#define SF_MMR          (SF_BASE + 0x0C)        /*!< \brief Memory mode register address. */
+#define SF_RAMWU                0x00000001      /*!< \brief Internal extended RAM write allowed. */
+/*@}*/
+
+/*! \name Protect Mode Register */
+/*@{*/
+#define SF_PMR          (SF_BASE + 0x18)        /*!< \brief Protect mode register address. */
+#define SF_AIC                  0x00000020      /*!< \brief AIC runs in protect mode. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Sf */
+
+#endif                          /* _ARCH_ARM_AT91_SF_H_ */
+

include/arch/arm/at91_smc.h

@@ -0,0 +1,118 @@
+#ifndef _ARCH_ARM_AT91_SMC_H_
+#define	_ARCH_ARM_AT91_SMC_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_smc.h
+ * \brief AT91 static memory controller.
+ *
+ * \verbatim
+ *
+ * $Log: at91_smc.h,v $
+ * Revision 1.1  2006/08/31 19:10:38  haraldkipp
+ * New peripheral register definitions for the AT91SAM9260.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Smc
+ */
+/*@{*/
+
+/*! \name SMC Setup Register */
+/*@{*/
+#define SMC_SETUP(cs)   (SMC_BASE + 0x10 * cs + 0x00)   /*!< \brief SMC setup register address. */
+#define SMC_NWE_SETUP                       0x0000003F  /*!< \brief NWE setup length mask. */
+#define SMC_NWE_SETUP_LSB                           0   /*!< \brief NWE setup length LSB. */
+#define SMC_NCS_WR_SETUP                    0x00003F00  /*!< \brief NCS setup length in write access mask. */
+#define SMC_NCS_WR_SETUP_LSB                        8   /*!< \brief NCS setup length in write access LSB. */
+#define SMC_NRD_SETUP                       0x003F0000  /*!< \brief NRD setup length mask. */
+#define SMC_NRD_SETUP_LSB                           16  /*!< \brief NRD setup length LSB. */
+#define SMC_NCS_RD_SETUP                    0x3F000000  /*!< \brief NCS setup length in read access mask. */
+#define SMC_NCS_RD_SETUP_LSB                        24  /*!< \brief NCS setup length in read access LSB. */
+/*@}*/
+
+/*! \name SMC Pulse Register */
+/*@{*/
+#define SMC_PULSE(cs)   (SMC_BASE + 0x10 * cs + 0x04)   /*!< \brief SMC pulse register address. */
+#define SMC_NWE_PULSE                       0x0000003F  /*!< \brief NWE pulse length mask. */
+#define SMC_NWE_PULSE_LSB                           0   /*!< \brief NWE pulse length LSB. */
+#define SMC_NCS_WR_PULSE                    0x00003F00  /*!< \brief NCS pulse length in write access mask. */
+#define SMC_NCS_WR_PULSE_LSB                        8   /*!< \brief NCS pulse length in write access LSB. */
+#define SMC_NRD_PULSE                       0x003F0000  /*!< \brief NRD pulse length mask. */
+#define SMC_NRD_PULSE_LSB                           16  /*!< \brief NRD pulse length LSB. */
+#define SMC_NCS_RD_PULSE                    0x3F000000  /*!< \brief NCS pulse length in read access mask. */
+#define SMC_NCS_RD_PULSE_LSB                        24  /*!< \brief NCS pulse length in read access LSB. */
+/*@}*/
+
+/*! \name SMC Cycle Register */
+/*@{*/
+#define SMC_CYCLE(cs)   (SMC_BASE + 0x10 * cs + 0x08)   /*!< \brief SMC cycle register address. */
+#define SMC_NWE_CYCLE                       0x000001FF  /*!< \brief Total write cycle length mask. */
+#define SMC_NWE_CYCLE_LSB                           0   /*!< \brief Total write cycle length LSB. */
+#define SMC_NRD_CYCLE                       0x01FF0000  /*!< \brief Total read cycle length mask. */
+#define SMC_NRD_CYCLE_LSB                           16  /*!< \brief Total read cycle length LSB. */
+/*@}*/
+
+/*! \name SMC Mode Register */
+/*@{*/
+#define SMC_MODE(cs)    (SMC_BASE + 0x10 * cs + 0x0C)   /*!< \brief SMC mode register address. */
+#define SMC_READ_MODE                       0x00000001  /*!< \brief Read operation mode. */
+#define SMC_WRITE_MODE                      0x00000002  /*!< \brief Write operation mode. */
+#define SMC_EXNW_MODE                       0x00000030  /*!< \brief NWAIT mode mask. */
+#define SMC_EXNW_MODE_DISABLED              0x00000000  /*!< \brief NWAIT mode mask. */
+#define SMC_EXNW_MODE_FROZEN                0x00000020  /*!< \brief NWAIT mode mask. */
+#define SMC_EXNW_MODE_READY                 0x00000030  /*!< \brief NWAIT mode mask. */
+#define SMC_BAT                             0x00000100  /*!< \brief Byte access mode. */
+#define SMC_DBW                             0x00003000  /*!< \brief Data bus width. */
+#define SMC_DBW_8                           0x00000000  /*!< \brief 8-bit data bus. */
+#define SMC_DBW_16                          0x00001000  /*!< \brief 16-bit data bus. */
+#define SMC_DBW_32                          0x00002000  /*!< \brief 32-bit data bus. */
+#define SMC_TDF_CYCLES                      0x000F0000  /*!< \brief Data float time mask. */
+#define SMC_TDF_CYCLES_LSB                  0x000F0000  /*!< \brief Data float time LSB. */
+#define SMC_TDF_MODE                        0x00100000  /*!< \brief TDF optimization. */
+#define SMC_PMEN                            0x01000000  /*!< \brief Page mode enable. */
+#define SMC_PS                              0x30000000  /*!< \brief Page size mask. */
+#define SMC_PS_4                            0x30000000  /*!< \brief 4-byte page. */
+#define SMC_PS_8                            0x30000000  /*!< \brief 8-byte page. */
+#define SMC_PS_16                           0x30000000  /*!< \brief 16-byte page. */
+#define SMC_PS_32                           0x30000000  /*!< \brief 32-byte page. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Smc */
+
+
+#endif                          /* _ARCH_ARM_AT91_SMC_H_ */

include/arch/arm/at91_spi.h

@@ -0,0 +1,229 @@
+#ifndef _ARCH_ARM_AT91_SPI_H_
+#define _ARCH_ARM_AT91_SPI_H_
+
+/*
+ * Copyright (C)
+ */
+
+/*!
+ * \file arch/arm/at91_spi.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_spi.h,v $
+ * Revision 1.5  2006/09/29 12:30:31  haraldkipp
+ * Register offsets added.
+ *
+ * Revision 1.4  2006/08/31 19:11:46  haraldkipp
+ * Bits per transfer definitions added.
+ *
+ * Revision 1.3  2006/08/05 11:54:45  haraldkipp
+ * PDC registers added.
+ *
+ * Revision 1.2  2006/07/26 11:22:31  haraldkipp
+ * Added missing bit definitions.
+ *
+ * Revision 1.1  2006/07/21 09:03:56  haraldkipp
+ * Added SPI support, kindly contributed by Andras Albert.
+ *
+ * Revision 1.1
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Spi
+ */
+/*@{*/
+
+/*! \name SPI Control Register */
+/*@{*/
+#define	SPI_CR_OFF	    0x00000000  /*!< \brief Control register offset. */
+
+#define SPI_SPIEN       0x00000001  /*!< \brief SPI enable. */
+#define SPI_SPIDIS      0x00000002  /*!< \brief SPI disable. */
+#define SPI_SWRST       0x00000080  /*!< \brief Software reset. */
+#define SPI_LASTXFER    0x01000000  /*!< \brief Last transfer. */
+/*@}*/
+
+/*! \name SPI Mode Register */
+/*@{*/
+#define SPI_MR_OFF		0x00000004  /*!< \brief Mode register offset. */
+
+#define SPI_MSTR        0x00000001  /*!< \brief Master mode. */
+#define SPI_PS          0x00000002  /*!< \brief Peripheral select. */
+#define SPI_PCSDEC      0x00000004  /*!< \brief Chip select decode. */
+#define SPI_FDIV        0x00000008  /*!< \brief Clock selection. */
+#define SPI_MODFDIS     0x00000010  /*!< \brief Mode fault detection. */
+#define SPI_LLB         0x00000080  /*!< \brief Local loopback enable. */
+#define SPI_PCS         0x000F0000  /*!< \brief Peripheral chip select mask. */
+#define SPI_PCS_0       0x000E0000  /*!< \brief Peripheral chip select 0. */
+#define SPI_PCS_1       0x000D0000  /*!< \brief Peripheral chip select 1. */
+#define SPI_PCS_2       0x000B0000  /*!< \brief Peripheral chip select 2. */
+#define SPI_PCS_3       0x00070000  /*!< \brief Peripheral chip select 3. */
+#define SPI_PCS_LSB             16  /*!< \brief Least significant bit of peripheral chip select. */
+#define SPI_DLYBCS      0xFF000000  /*!< \brief Mask for delay between chip selects. */
+#define SPI_DLYBCS_LSB          24  /*!< \brief Least significant bit of delay between chip selects. */
+/*@}*/
+
+/*! \name SPI Receive Data Register */
+/*@{*/
+#define SPI_RDR_OFF		0x00000008  /*!< \brief Receive data register offset. */
+
+#define SPI_RD          0x0000FFFF  /*!< \brief Receive data mask. */
+#define SPI_RD_LSB              0   /*!< \brief Least significant bit of receive data. */
+/*@}*/
+
+/*! \name SPI Transmit Data Register */
+/*@{*/
+#define SPI_TDR_OFF		0x0000000C  /*!< \brief Transmit data register offset. */
+
+#define SPI_TD          0x0000FFFF  /*!< \brief Transmit data mask. */
+#define SPI_TD_LSB              0   /*!< \brief Least significant bit of transmit data. */
+/*@}*/
+
+/*! \name SPI Status and Interrupt Register */
+/*@{*/
+#define SPI_SR_OFF		0x00000010  /*!< \brief Status register offset. */
+#define SPI_IER_OFF		0x00000014  /*!< \brief Interrupt enable register offset. */
+#define SPI_IDR_OFF		0x00000018  /*!< \brief Interrupt disable register offset. */
+#define SPI_IMR_OFF		0x0000001C  /*!< \brief Interrupt mask register offset. */
+
+#define SPI_RDRF        0x00000001  /*!< \brief Receive data register full. */
+#define SPI_TDRE        0x00000002  /*!< \brief Transmit data register empty. */
+#define SPI_MODF        0x00000004  /*!< \brief Mode fault error. */
+#define SPI_OVRES       0x00000008  /*!< \brief Overrun error status. */
+#define SPI_ENDRX       0x00000010  /*!< \brief End of RX buffer. */
+#define SPI_ENDTX       0x00000020  /*!< \brief End of TX buffer. */
+#define SPI_RXBUFF      0x00000040  /*!< \brief RX buffer full. */
+#define SPI_TXBUFE      0x00000080  /*!< \brief TX buffer empty. */
+#define SPI_NSSR        0x00000100  /*!< \brief NSS rising. */
+#define SPI_TXEMPTY     0x00000200  /*!< \brief Transmission register empty. */
+#define SPI_SPIENS      0x00010000  /*!< \brief SPI enable status. */
+/*@}*/
+
+/*! \name SPI Chip Select Registers */
+/*@{*/
+#define SPI_CSR0_OFF	0x00000030  /*!< \brief Chip select register 0 offset. */
+#define SPI_CSR1_OFF	0x00000034  /*!< \brief Chip select register 1 offset. */
+#define SPI_CSR2_OFF	0x00000038  /*!< \brief Chip select register 2 offset. */
+#define SPI_CSR3_OFF    0x0000003C  /*!< \brief Chip select register 3 offset. */
+
+#define SPI_CPOL        0x00000001  /*!< \brief Clock polarity. */
+#define SPI_NCPHA       0x00000002  /*!< \brief Clock phase. */
+#define SPI_CSAAT       0x00000008  /*!< \brief Chip select active after transfer. */
+#define SPI_BITS        0x000000F0  /*!< \brief Bits per transfer mask. */
+#define SPI_BITS_8      0x00000000  /*!< \brief 8 bits per transfer. */
+#define SPI_BITS_9      0x00000010  /*!< \brief 9 bits per transfer. */
+#define SPI_BITS_10     0x00000020  /*!< \brief 10 bits per transfer. */
+#define SPI_BITS_11     0x00000030  /*!< \brief 11 bits per transfer. */
+#define SPI_BITS_12     0x00000040  /*!< \brief 12 bits per transfer. */
+#define SPI_BITS_13     0x00000050  /*!< \brief 13 bits per transfer. */
+#define SPI_BITS_14     0x00000060  /*!< \brief 14 bits per transfer. */
+#define SPI_BITS_15     0x00000070  /*!< \brief 15 bits per transfer. */
+#define SPI_BITS_16     0x00000080  /*!< \brief 16 bits per transfer. */
+#define SPI_BITS_LSB            4   /*!< \brief Least significant bit of bits per transfer. */
+#define SPI_SCBR        0x0000FF00  /*!< \brief Serial clock baud rate mask. */
+#define SPI_SCBR_LSB            8   /*!< \brief Least significant bit of serial clock baud rate. */
+#define SPI_DLYBS       0x00FF0000  /*!< \brief Delay before SPCK mask. */
+#define SPI_DLYBS_LSB           16  /*!< \brief Least significant bit of delay before SPCK. */
+#define SPI_DLYBCT      0xFF000000  /*!< \brief Delay between consecutive transfers mask. */
+#define SPI_DLYBCT_LSB          24  /*!< \brief Least significant bit of delay between consecutive transfers. */
+/*@}*/
+
+/*! \name Single SPI Register Addresses */
+/*@{*/
+#if defined(SPI_BASE)
+#define SPI0_BASE   SPI_BASE
+#define	SPI_CR		SPI0_CR     /*!< \brief SPI Control Register Write-only. */
+#define SPI_MR		SPI0_MR     /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
+#define SPI_RDR		SPI0_RDR    /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
+#define SPI_TDR		SPI0_TDR    /*!< \brief SPI Transmit Data Register Write-only . */
+#define SPI_SR		SPI0_SR     /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
+#define SPI_IER		SPI0_IER    /*!< \brief SPI Interrupt Enable Register Write-only. */
+#define SPI_IDR		SPI0_IDR    /*!< \brief SPI Interrupt Disable Register Write-only. */
+#define SPI_IMR		SPI0_IMR    /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
+#define SPI_CSR0	SPI0_CSR0   /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
+#define SPI_CSR1	SPI0_CSR1   /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
+#define SPI_CSR2	SPI0_CSR2   /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
+#define SPI_CSR3	SPI0_CSR3   /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
+#if defined(SPI_HAS_PDC)
+#define SPI_RPR     SPI0_RPR    /*!< \brief PDC channel 0 receive pointer register. */
+#define SPI_RCR     SPI0_RCR    /*!< \brief PDC channel 0 receive counter register. */
+#define SPI_TPR     SPI0_TPR    /*!< \brief PDC channel 0 transmit pointer register. */
+#define SPI_TCR     SPI0_TCR    /*!< \brief PDC channel 0 transmit counter register. */
+#define SPI_RNPR    SPI0_RNPR   /*!< \brief PDC channel 0 receive next pointer register. */
+#define SPI_RNCR    SPI0_RNCR   /*!< \brief PDC channel 0 receive next counter register. */
+#define SPI_TNPR    SPI0_TNPR   /*!< \brief PDC channel 0 transmit next pointer register. */
+#define SPI_TNCR    SPI0_TNCR   /*!< \brief PDC channel 0 transmit next counter register. */
+#define SPI_PTCR    SPI0_PTCR   /*!< \brief PDC channel 0 transfer control register. */
+#define SPI_PTSR    SPI0_PTSR   /*!< \brief PDC channel 0 transfer status register. */
+#endif /* SPI_HAS_PDC */
+#endif /* SPI_BASE */
+/*@}*/
+
+/*! \name SPI 0 Register Addresses */
+/*@{*/
+#if defined(SPI0_BASE)
+#define	SPI0_CR		(SPI0_BASE + SPI_CR_OFF)        /*!< \brief SPI Control Register Write-only. */
+#define SPI0_MR		(SPI0_BASE + SPI_MR_OFF)        /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
+#define SPI0_RDR	(SPI0_BASE + SPI_RDR_OFF)       /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
+#define SPI0_TDR	(SPI0_BASE + SPI_TDR_OFF)       /*!< \brief SPI Transmit Data Register Write-only . */
+#define SPI0_SR		(SPI0_BASE + SPI_SR_OFF)        /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
+#define SPI0_IER	(SPI0_BASE + SPI_IER_OFF)       /*!< \brief SPI Interrupt Enable Register Write-only. */
+#define SPI0_IDR	(SPI0_BASE + SPI_IDR_OFF)       /*!< \brief SPI Interrupt Disable Register Write-only. */
+#define SPI0_IMR	(SPI0_BASE + SPI_IMR_OFF)       /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
+#define SPI0_CSR0	(SPI0_BASE + SPI_CSR0_OFF)      /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
+#define SPI0_CSR1	(SPI0_BASE + SPI_CSR1_OFF)      /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
+#define SPI0_CSR2	(SPI0_BASE + SPI_CSR2_OFF)      /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
+#define SPI0_CSR3	(SPI0_BASE + SPI_CSR3_OFF)      /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
+#if defined(SPI_HAS_PDC)
+#define SPI0_RPR    (SPI0_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC channel 0 receive pointer register. */
+#define SPI0_RCR    (SPI0_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC channel 0 receive counter register. */
+#define SPI0_TPR    (SPI0_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC channel 0 transmit pointer register. */
+#define SPI0_TCR    (SPI0_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC channel 0 transmit counter register. */
+#define SPI0_RNPR   (SPI0_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC channel 0 receive next pointer register. */
+#define SPI0_RNCR   (SPI0_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC channel 0 receive next counter register. */
+#define SPI0_TNPR   (SPI0_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC channel 0 transmit next pointer register. */
+#define SPI0_TNCR   (SPI0_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC channel 0 transmit next counter register. */
+#define SPI0_PTCR   (SPI0_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC channel 0 transfer control register. */
+#define SPI0_PTSR   (SPI0_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC channel 0 transfer status register. */
+#endif /* SPI_HAS_PDC */
+#endif /* SPI0_BASE */
+/*@}*/
+
+/*! \name SPI 1 Register Addresses */
+/*@{*/
+#if defined(SPI1_BASE)
+#define	SPI1_CR		(SPI1_BASE + SPI_CR_OFF)        /*!< \brief SPI Control Register Write-only. */
+#define SPI1_MR		(SPI1_BASE + SPI_MR_OFF)        /*!< \brief SPI Mode Register Read/Write Reset=0x0. */
+#define SPI1_RDR	(SPI1_BASE + SPI_RDR_OFF)       /*!< \brief SPI Receive Data Register Read-only Reset=0x0. */
+#define SPI1_TDR	(SPI1_BASE + SPI_TDR_OFF)       /*!< \brief SPI Transmit Data Register Write-only . */
+#define SPI1_SR		(SPI1_BASE + SPI_SR_OFF)        /*!< \brief SPI Status Register Read-only Reset=0x000000F0. */
+#define SPI1_IER	(SPI1_BASE + SPI_IER_OFF)       /*!< \brief SPI Interrupt Enable Register Write-only. */
+#define SPI1_IDR	(SPI1_BASE + SPI_IDR_OFF)       /*!< \brief SPI Interrupt Disable Register Write-only. */
+#define SPI1_IMR	(SPI1_BASE + SPI_IMR_OFF)       /*!< \brief SPI Interrupt Mask Register Read-only Reset=0x0. */
+#define SPI1_CSR0	(SPI1_BASE + SPI_CSR0_OFF)      /*!< \brief SPI Chip Select Register 0 Read/Write Reset=0x0. */
+#define SPI1_CSR1	(SPI1_BASE + SPI_CSR1_OFF)      /*!< \brief SPI Chip Select Register 1 Read/Write Reset=0x0. */
+#define SPI1_CSR2	(SPI1_BASE + SPI_CSR2_OFF)      /*!< \brief SPI Chip Select Register 2 Read/Write Reset=0x0. */
+#define SPI1_CSR3	(SPI1_BASE + SPI_CSR3_OFF)      /*!< \brief SPI Chip Select Register 3 Read/Write Reset=0x0. */
+#if defined(SPI_HAS_PDC)
+#define SPI1_RPR    (SPI1_BASE + PERIPH_RPR_OFF)    /*!< \brief PDC channel 1 receive pointer register. */
+#define SPI1_RCR    (SPI1_BASE + PERIPH_RCR_OFF)    /*!< \brief PDC channel 1 receive counter register. */
+#define SPI1_TPR    (SPI1_BASE + PERIPH_TPR_OFF)    /*!< \brief PDC channel 1 transmit pointer register. */
+#define SPI1_TCR    (SPI1_BASE + PERIPH_TCR_OFF)    /*!< \brief PDC channel 1 transmit counter register. */
+#define SPI1_RNPR   (SPI1_BASE + PERIPH_RNPR_OFF)   /*!< \brief PDC channel 1 receive next pointer register. */
+#define SPI1_RNCR   (SPI1_BASE + PERIPH_RNCR_OFF)   /*!< \brief PDC channel 1 receive next counter register. */
+#define SPI1_TNPR   (SPI1_BASE + PERIPH_TNPR_OFF)   /*!< \brief PDC channel 1 transmit next pointer register. */
+#define SPI1_TNCR   (SPI1_BASE + PERIPH_TNCR_OFF)   /*!< \brief PDC channel 1 transmit next counter register. */
+#define SPI1_PTCR   (SPI1_BASE + PERIPH_PTCR_OFF)   /*!< \brief PDC channel 1 transfer control register. */
+#define SPI1_PTSR   (SPI1_BASE + PERIPH_PTSR_OFF)   /*!< \brief PDC channel 1 transfer status register. */
+#endif /* SPI_HAS_PDC */
+#endif /* SPI1_BASE */
+/*@}*/
+
+/*@} xgNutArchArmAt91Spi */
+
+#endif  /* _ARCH_ARM_AT91_SPI_H_ */

include/arch/arm/at91_ssc.h

@@ -0,0 +1,276 @@
+#ifndef _ARCH_ARM_AT91_SSC_H_
+#define _ARCH_ARM_AT91_SSC_H_
+
+/*
+ * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_ssc.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_ssc.h,v $
+ * Revision 1.4  2007/02/15 16:20:38  haraldkipp
+ * Wrong SSC clock naming broke external clock feeding. Fixed.
+ *
+ * Revision 1.3  2006/09/29 12:44:17  haraldkipp
+ * Just sorted lines a bit.
+ *
+ * Revision 1.2  2006/08/31 19:12:13  haraldkipp
+ * Frame sync definitions added.
+ *
+ * Revision 1.1  2006/08/05 11:58:54  haraldkipp
+ * First release.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Ssc
+ */
+/*@{*/
+
+/*! \name SSC Control Register */
+/*@{*/
+#define SSC_CR_OFF                  0x00000000  /*!< \brief Control register offset. */
+#define SSC_CR      (SSC_BASE + SSC_CR_OFF)     /*!< \brief Control register address. */
+#define SSC_RXEN                    0x00000001  /*!< \brief Receive enable. */
+#define SSC_RXDIS                   0x00000002  /*!< \brief Receive disable. */
+#define SSC_TXEN                    0x00000100  /*!< \brief Transmit enable. */
+#define SSC_TXDIS                   0x00000200  /*!< \brief Transmit disable. */
+#define SSC_SWRST                   0x00008000  /*!< \brief Software reset. */
+/*@}*/
+
+/*! \name SSC Clock Mode Register */
+/*@{*/
+#define SSC_CMR_OFF                 0x00000004  /*!< \brief Clock mode register offset. */
+#define SSC_CMR     (SSC_BASE + SSC_CMR_OFF)    /*!< \brief Clock mode register address. */
+#define SSC_DIV_LSB                         0   /*!< \brief Least significant bit of clock divider. */
+#define SSC_DIV                     0x00000FFF  /*!< \brief Clock divider. */
+/*@}*/
+
+/*! \name SSC Receive/Transmit Clock Mode Register */
+/*@{*/
+#define SSC_RCMR_OFF                0x00000010  /*!< \brief Receive clock mode register offset. */
+#define SSC_RCMR    (SSC_BASE + SSC_RCMR_OFF)   /*!< \brief Receive clock mode register address. */
+#define SSC_TCMR_OFF                0x00000018  /*!< \brief Transmit clock mode register offset. */
+#define SSC_TCMR    (SSC_BASE + SSC_TCMR_OFF)   /*!< \brief Transmit clock mode register address. */
+
+#define SSC_CKS                     0x00000003  /*!< \brief Receive clock selection. */
+#define SSC_CKS_DIV                 0x00000000  /*!< \brief Divided clock. */
+#define SSC_CKS_RK                  0x00000001  /*!< \brief RK clock signal. */
+#define SSC_CKS_TK                  0x00000002  /*!< \brief TK pin. */
+#define SSC_CKO                     0x0000001C  /*!< \brief Receive clock output mode selection. */
+#define SSC_CKO_NONE                0x00000000  /*!< \brief None. */
+#define SSC_CKO_CONT                0x00000004  /*!< \brief Continous receive clock. */
+#define SSC_CKO_TRAN                0x00000008  /*!< \brief Receive clock only during data transfers. */
+#define SSC_CKI                     0x00000020  /*!< \brief Receive clock inversion. */
+#define SSC_CKG                     0x000000C0  /*!< \brief Receive clock gating selection. */
+#define SSC_CKG_NONE                0x00000000  /*!< \brief None, continous clock. */
+#define SSC_CKG_RFL                 0x00000040  /*!< \brief Continous receive clock. */
+#define SSC_CKG_RFH                 0x00000080  /*!< \brief Receive clock only during data transfers. */
+#define SSC_START                   0x00000F00  /*!< \brief Receive start selection. */
+#define SSC_START_CONT              0x00000000  /*!< \brief Receive start as soon as enabled. */
+#define SSC_START_TX                0x00000100  /*!< \brief Receive start on transmit start. */
+#define SSC_START_LOW_RF            0x00000200  /*!< \brief Receive start on low level RF. */
+#define SSC_START_HIGH_RF           0x00000300  /*!< \brief Receive start on high level RF. */
+#define SSC_START_FALL_RF           0x00000400  /*!< \brief Receive start on falling edge RF. */
+#define SSC_START_RISE_RF           0x00000500  /*!< \brief Receive start on rising edge RF. */
+#define SSC_START_LEVEL_RF          0x00000600  /*!< \brief Receive start on any RF level change. */
+#define SSC_START_EDGE_RF           0x00000700  /*!< \brief Receive start on any RF edge. */
+#define SSC_START_COMP0             0x00000800  /*!< \brief Receive on compare 0. */
+#define SSC_STOP                    0x00001000  /*!< \brief Receive stop selection. */
+#define SSC_STTDLY                  0x00FF0000  /*!< \brief Receive start delay. */
+#define SSC_STTDLY_LSB                      16  /*!< \brief Least significant bit of receive start delay. */
+#define SSC_PERIOD                  0xFF000000  /*!< \brief Receive period divider selection. */
+#define SSC_PERIOD_LSB                      24  /*!< \brief Least significant bit of receive period divider selection. */
+/*@}*/
+
+/*! \name SSC Receive/Transmit Frame Mode Registers */
+/*@{*/
+#define SSC_RFMR_OFF                0x00000014  /*!< \brief Receive frame mode register offset. */
+#define SSC_RFMR    (SSC_BASE + SSC_RFMR_OFF)   /*!< \brief Receive frame mode register address. */
+#define SSC_TFMR_OFF                0x0000001C  /*!< \brief Transmit frame mode register offset. */
+#define SSC_TFMR    (SSC_BASE + SSC_TFMR_OFF)   /*!< \brief Transmit frame mode register address. */
+
+#define SSC_DATLEN                  0x0000001F  /*!< \brief Data length. */
+#define SSC_DATLEN_LSB                      0   /*!< \brief Least significant bit of data length. */
+#define SSC_LOOP                    0x00000020  /*!< \brief Loop mode. */
+#define SSC_MSBF                    0x00000080  /*!< \brief Most significant bit first. */
+#define SSC_DATNB                   0x00000F00  /*!< \brief Data number per frame. */
+#define SSC_DATNB_LSB                       8   /*!< \brief Least significant bit of data number per frame. */
+#define SSC_FSLEN                   0x000F0000  /*!< \brief Receive frame sync. length. */
+#define SSC_FSLEN_LSB                       16  /*!< \brief Least significant bit of receive frame sync. length. */
+#define SSC_FSOS                    0x00700000  /*!< \brief Receive frame sync. output selection. */
+#define SSC_FSOS_NONE               0x00000000  /*!< \brief No frame sync. Line set to input. */
+#define SSC_FSOS_NEGATIVE           0x00100000  /*!< \brief Negative pulse. */
+#define SSC_FSOS_POSITIVE           0x00200000  /*!< \brief Positive pulse. */
+#define SSC_FSOS_LOW                0x00300000  /*!< \brief Low during transfer. */
+#define SSC_FSOS_HIGH               0x00400000  /*!< \brief High during transfer. */
+#define SSC_FSOS_TOGGLE             0x00500000  /*!< \brief Toggling at each start. */
+#define SSC_FSEDGE                  0x01000000  /*!< \brief Frame sync. edge detection. */
+/*@}*/
+
+/*! \name SSC Receive Holding Register */
+/*@{*/
+#define SSC_RHR_OFF                 0x00000020  /*!< \brief Receive holding register offset. */
+#define SSC_RHR     (SSC_BASE + SSC_RHR_OFF)    /*!< \brief Receive holding register address. */
+/*@}*/
+
+/*! \name SSC Transmit Holding Register */
+/*@{*/
+#define SSC_THR_OFF                 0x00000024  /*!< \brief Transmit holding register offset. */
+#define SSC_THR     (SSC_BASE + SSC_THR_OFF)    /*!< \brief Transmit holding register address. */
+/*@}*/
+
+/*! \name SSC Receive Sync. Holding Register */
+/*@{*/
+#define SSC_RSHR_OFF                0x00000030  /*!< \brief Receive sync. holding register offset. */
+#define SSC_RSHR    (SSC_BASE + SSC_RSHR_OFF)   /*!< \brief Receive sync. holding register address. */
+/*@}*/
+
+/*! \name SSC Transmit Sync. Holding Register */
+/*@{*/
+#define SSC_TSHR_OFF                0x00000034  /*!< \brief Transmit sync. holding register offset. */
+#define SSC_TSHR    (SSC_BASE + SSC_TSHR_OFF)   /*!< \brief Transmit sync. holding register address. */
+/*@}*/
+
+/*! \name SSC Receive Compare 0 Register */
+/*@{*/
+#define SSC_RC0R_OFF                0x00000038  /*!< \brief Receive compare 0 register offset. */
+#define SSC_RC0R    (SSC_BASE + SSC_RC0R_OFF)   /*!< \brief Receive compare 0 register address. */
+/*@}*/
+
+/*! \name SSC Receive Compare 1 Register */
+/*@{*/
+#define SSC_RC1R_OFF                0x0000003C  /*!< \brief Receive compare 1 register offset. */
+#define SSC_RC1R    (SSC_BASE + SSC_RC1R_OFF)   /*!< \brief Receive compare 1 register address. */
+/*@}*/
+
+/*! \name SSC Status Register */
+/*@{*/
+#define SSC_SR_OFF                  0x00000040  /*!< \brief Status register offset. */
+#define SSC_SR      (SSC_BASE + SSC_SR_OFF)     /*!< \brief Status register address. */
+#define SSC_TXRDY                   0x00000001  /*!< \brief Transmit ready. */
+#define SSC_TXEMPTY                 0x00000002  /*!< \brief Transmit empty. */
+#define SSC_ENDTX                   0x00000004  /*!< \brief End of transmission. */
+#define SSC_TXBUFE                  0x00000008  /*!< \brief Transmit buffer empty. */
+#define SSC_RXRDY                   0x00000010  /*!< \brief Receive ready. */
+#define SSC_OVRUN                   0x00000020  /*!< \brief Receive overrun. */
+#define SSC_ENDRX                   0x00000040  /*!< \brief End of receiption. */
+#define SSC_RXBUFF                  0x00000080  /*!< \brief Receive buffer full. */
+#define SSC_CP0                     0x00000100  /*!< \brief Compare 0. */
+#define SSC_CP1                     0x00000200  /*!< \brief Compare 1. */
+#define SSC_TXSYN                   0x00000400  /*!< \brief Transmit sync. */
+#define SSC_RXSYN                   0x00000800  /*!< \brief Receive sync. */
+#define SSC_TXENA                   0x00010000  /*!< \brief Transmit enable. */
+#define SSC_RXENA                   0x00020000  /*!< \brief Receive enable. */
+/*@}*/
+
+/*! \name SSC Interrupt Enable Register */
+/*@{*/
+#define SSC_IER_OFF                 0x00000044  /*!< \brief Interrupt enable register offset. */
+#define SSC_IER     (SSC_BASE + SSC_IER_OFF)    /*!< \brief Interrupt enable register address. */
+/*@}*/
+
+/*! \name SSC Interrupt Disable Register */
+/*@{*/
+#define SSC_IDR_OFF                 0x00000048  /*!< \brief Interrupt disable register offset. */
+#define SSC_IDR     (SSC_BASE + SSC_IDR_OFF)    /*!< \brief Interrupt disable register address. */
+/*@}*/
+
+/*! \name SSC Interrupt Mask Register */
+/*@{*/
+#define SSC_IMR_OFF                 0x0000004C  /*!< \brief Interrupt mask register offset. */
+#define SSC_IMR     (SSC_BASE + SSC_IMR_OFF)    /*!< \brief Interrupt mask register address. */
+/*@}*/
+
+#if defined(SSC_HAS_PDC)
+
+/*! \name SSC Receive Pointer Register */
+/*@{*/
+#define SSC_RPR    (SSC_BASE + PERIPH_RPR_OFF)  /*!< \brief PDC receive pointer register address. */
+/*@}*/
+
+/*! \name SSC Receive Counter Register */
+/*@{*/
+#define SSC_RCR    (SSC_BASE + PERIPH_RCR_OFF)  /*!< \brief PDC receive counter register address. */
+/*@}*/
+
+/*! \name SSC Transmit Pointer Register */
+/*@{*/
+#define SSC_TPR    (SSC_BASE + PERIPH_TPR_OFF)  /*!< \brief PDC transmit pointer register address. */
+/*@}*/
+
+/*! \name SSC Transmit Counter Register */
+/*@{*/
+#define SSC_TCR    (SSC_BASE + PERIPH_TCR_OFF)  /*!< \brief PDC transmit counter register address. */
+/*@}*/
+
+/*! \name SSC Receive Next Pointer Register */
+/*@{*/
+#define SSC_RNPR   (SSC_BASE + PERIPH_RNPR_OFF) /*!< \brief PDC receive next pointer register address. */
+/*@}*/
+
+/*! \name SSC Receive Next Counter Register */
+/*@{*/
+#define SSC_RNCR   (SSC_BASE + PERIPH_RNCR_OFF) /*!< \brief PDC receive next counter register address. */
+/*@}*/
+
+/*! \name SSC Transmit Next Pointer Register */
+/*@{*/
+#define SSC_TNPR   (SSC_BASE + PERIPH_TNPR_OFF) /*!< \brief PDC transmit next pointer register address. */
+/*@}*/
+
+/*! \name SSC Transmit Next Counter Register */
+/*@{*/
+#define SSC_TNCR   (SSC_BASE + PERIPH_TNCR_OFF) /*!< \brief PDC transmit next counter register address. */
+/*@}*/
+
+/*! \name SSC Transfer Control Register */
+/*@{*/
+#define SSC_PTCR   (SSC_BASE + PERIPH_PTCR_OFF) /*!< \brief PDC transfer control register address. */
+/*@}*/
+
+/*! \name SSC Transfer Status Register */
+/*@{*/
+#define SSC_PTSR   (SSC_BASE + PERIPH_PTSR_OFF) /*!< \brief PDC transfer status register address. */
+/*@}*/
+
+#endif
+
+/*@} xgNutArchArmAt91Ssc */
+
+
+#endif                          /* _ARCH_ARM_AT91_SSC_H_ */

include/arch/arm/at91_tc.h

@@ -0,0 +1,270 @@
+#ifndef _ARCH_ARM_AT91_TC_H_
+#define _ARCH_ARM_AT91_TC_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_tc.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_tc.h,v $
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Tc
+ */
+/*@{*/
+
+/*! \name Timer Counter Control Register */
+/*@{*/
+#define TC0_CCR         (TC_BASE + 0x00)        /*!< \brief Channel 0 control register address. */
+#define TC1_CCR         (TC_BASE + 0x40)        /*!< \brief Channel 1 control register address. */
+#define TC2_CCR         (TC_BASE + 0x80)        /*!< \brief Channel 2 control register address. */
+#define TC_CLKEN                0x00000001      /*!< \brief Clock enable command. */
+#define TC_CLKDIS               0x00000002      /*!< \brief Clock disable command. */
+#define TC_SWTRG                0x00000004      /*!< \brief Software trigger command. */
+/*@}*/
+
+/*! \name Timer Counter Channel Mode Register */
+/*@{*/
+#define TC0_CMR         (TC_BASE + 0x04)        /*!< \brief Channel 0 mode register address. */
+#define TC1_CMR         (TC_BASE + 0x44)        /*!< \brief Channel 1 mode register address. */
+#define TC2_CMR         (TC_BASE + 0x84)        /*!< \brief Channel 2 mode register address. */
+
+#define TC_CLKS                 0x00000007      /*!< \brief Clock selection mask. */
+#define TC_CLKS_MCK2            0x00000000      /*!< \brief Selects MCK / 2. */
+#define TC_CLKS_MCK8            0x00000001      /*!< \brief Selects MCK / 8. */
+#define TC_CLKS_MCK32           0x00000002      /*!< \brief Selects MCK / 32. */
+#define TC_CLKS_MCK128          0x00000003      /*!< \brief Selects MCK / 128. */
+#define TC_CLKS_MCK1024         0x00000004      /*!< \brief Selects MCK / 1024. */
+#define TC_CLKS_XC0             0x00000005      /*!< \brief Selects external clock 0. */
+#define TC_CLKS_XC1             0x00000006      /*!< \brief Selects external clock 1. */
+#define TC_CLKS_XC2             0x00000007      /*!< \brief Selects external clock 2. */
+
+#define TC_CLKI                 0x00000008      /*!< \brief Increments on falling edge. */
+
+#define TC_BURST                0x00000030      /*!< \brief Burst signal selection mask. */
+#define TC_BURST_NONE           0x00000000      /*!< \brief Clock is not gated by an external signal. */
+#define TC_BUSRT_XC0            0x00000010      /*!< \brief ANDed with external clock 0. */
+#define TC_BURST_XC1            0x00000020      /*!< \brief ANDed with external clock 1. */
+#define TC_BURST_XC2            0x00000030      /*!< \brief ANDed with external clock 2. */
+
+#define TC_CPCTRG               0x00004000      /*!< \brief RC Compare Enable Trigger Enable. */
+
+#define TC_WAVE                 0x00008000      /*!< \brief Selects waveform mode. */
+#define TC_CAPT                 0x00000000      /*!< \brief Selects capture mode. */
+/*@}*/
+
+/*! \name Capture Mode */
+/*@{*/
+#define TC_LDBSTOP              0x00000040      /*!< \brief Counter clock stopped on RB loading. */
+#define TC_LDBDIS               0x00000080      /*!< \brief Counter clock disabled on RB loading. */
+
+#define TC_ETRGEDG              0x00000300      /*!< \brief External trigger edge selection mask. */
+#define TC_ETRGEDG_RISING_EDGE  0x00000100      /*!< \brief Trigger on external rising edge. */
+#define TC_ETRGEDG_FALLING_EDGE 0x00000200      /*!< \brief Trigger on external falling edge. */
+#define TC_ETRGEDG_BOTH_EDGE    0x00000300      /*!< \brief Trigger on both external edges. */
+
+#define TC_ABETRG               0x00000400      /*!< \brief TIOA or TIOB external trigger selection mask. */
+#define TC_ABETRG_TIOB          0x00000000      /*!< \brief TIOB used as an external trigger. */
+#define TC_ABETRG_TIOA          0x00000400      /*!< \brief TIOA used as an external trigger. */
+
+#define TC_LDRA                 0x00030000      /*!< \brief RA loading selection mask. */
+#define TC_LDRA_RISING_EDGE     0x00010000      /*!< \brief Load RA on rising edge of TIOA. */
+#define TC_LDRA_FALLING_EDGE    0x00020000      /*!< \brief Load RA on falling edge of TIOA. */
+#define TC_LDRA_BOTH_EDGE       0x00030000      /*!< \brief Load RA on any edge of TIOA. */
+
+#define TC_LDRB                 0x000C0000      /*!< \brief RB loading selection mask. */
+#define TC_LDRB_RISING_EDGE     0x00040000      /*!< \brief Load RB on rising edge of TIOA. */
+#define TC_LDRB_FALLING_EDGE    0x00080000      /*!< \brief Load RB on falling edge of TIOA. */
+#define TC_LDRB_BOTH_EDGE       0x000C0000      /*!< \brief Load RB on any edge of TIOA. */
+
+/*@}*/
+
+/*! \name Waveform Mode */
+/*@{*/
+#define TC_CPCSTOP              0x00000040      /*!< \brief Counter clock stopped on RC compare. */
+#define TC_CPCDIS               0x00000080      /*!< \brief Counter clock disabled on RC compare. */
+
+#define TC_EEVTEDG              0x00000300      /*!< \brief External event edge selection mask. */
+#define TC_EEVTEDG_RISING_EDGE  0x00000100      /*!< \brief External event on rising edge.. */
+#define TC_EEVTEDG_FALLING_EDGE 0x00000200      /*!< \brief External event on falling edge.. */
+#define TC_EEVTEDG_BOTH_EDGE    0x00000300      /*!< \brief External event on any edge.. */
+
+#define TC_EEVT                 0x00000C00      /*!< \brief External event selection mask. */
+#define TC_EEVT_TIOB            0x00000000      /*!< \brief TIOB selected as external event. */
+#define TC_EEVT_XC0             0x00000400      /*!< \brief XC0 selected as external event. */
+#define TC_EEVT_XC1             0x00000800      /*!< \brief XC1 selected as external event. */
+#define TC_EEVT_XC2             0x00000C00      /*!< \brief XC2 selected as external event. */
+
+#define TC_ENETRG               0x00001000      /*!< \brief External event trigger enable. */
+
+#define TC_ACPA                 0x00030000      /*!< \brief Masks RA compare effect on TIOA. */
+#define TC_ACPA_SET_OUTPUT      0x00010000      /*!< \brief RA compare sets TIOA. */
+#define TC_ACPA_CLEAR_OUTPUT    0x00020000      /*!< \brief RA compare clears TIOA. */
+#define TC_ACPA_TOGGLE_OUTPUT   0x00030000      /*!< \brief RA compare toggles TIOA. */
+
+#define TC_ACPC                 0x000C0000      /*!< \brief Masks RC compare effect on TIOA. */
+#define TC_ACPC_SET_OUTPUT      0x00040000      /*!< \brief RC compare sets TIOA. */
+#define TC_ACPC_CLEAR_OUTPUT    0x00080000      /*!< \brief RC compare clears TIOA. */
+#define TC_ACPC_TOGGLE_OUTPUT   0x000C0000      /*!< \brief RC compare toggles TIOA. */
+
+#define TC_AEEVT                0x00300000      /*!< \brief Masks external event effect on TIOA. */
+#define TC_AEEVT_SET_OUTPUT     0x00100000      /*!< \brief External event sets TIOA. */
+#define TC_AEEVT_CLEAR_OUTPUT   0x00200000      /*!< \brief External event clears TIOA. */
+#define TC_AEEVT_TOGGLE_OUTPUT  0x00300000      /*!< \brief External event toggles TIOA. */
+
+#define TC_ASWTRG               0x00C00000      /*!< \brief Masks software trigger effect on TIOA. */
+#define TC_ASWTRG_SET_OUTPUT    0x00400000      /*!< \brief Software trigger sets TIOA. */
+#define TC_ASWTRG_CLEAR_OUTPUT  0x00800000      /*!< \brief Software trigger clears TIOA. */
+#define TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000      /*!< \brief Software trigger toggles TIOA. */
+
+#define TC_BCPB                 0x03000000      /*!< \brief Masks RB compare effect on TIOB. */
+#define TC_BCPB_SET_OUTPUT      0x01000000      /*!< \brief RB compare sets TIOB. */
+#define TC_BCPB_CLEAR_OUTPUT    0x02000000      /*!< \brief RB compare clears TIOB. */
+#define TC_BCPB_TOGGLE_OUTPUT   0x03000000      /*!< \brief RB compare toggles TIOB. */
+
+#define TC_BCPC                 0x0C000000      /*!< \brief Masks RC compare effect on TIOB. */
+#define TC_BCPC_SET_OUTPUT      0x04000000      /*!< \brief RC compare sets TIOB. */
+#define TC_BCPC_CLEAR_OUTPUT    0x08000000      /*!< \brief RC compare clears TIOB. */
+#define TC_BCPC_TOGGLE_OUTPUT   0x0C000000      /*!< \brief RC compare toggles TIOB. */
+
+#define TC_BEEVT                0x30000000      /*!< \brief Masks external event effect on TIOB. */
+#define TC_BEEVT_SET_OUTPUT     0x10000000      /*!< \brief External event sets TIOB. */
+#define TC_BEEVT_CLEAR_OUTPUT   0x20000000      /*!< \brief External event clears TIOB. */
+#define TC_BEEVT_TOGGLE_OUTPUT  0x30000000      /*!< \brief External event toggles TIOB. */
+
+#define TC_BSWTRG               0xC0000000      /*!< \brief Masks software trigger effect on TIOB. */
+#define TC_BSWTRG_SET_OUTPUT    0x40000000      /*!< \brief Software trigger sets TIOB. */
+#define TC_BSWTRG_CLEAR_OUTPUT  0x80000000      /*!< \brief Software trigger clears TIOB. */
+#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000      /*!< \brief Software trigger toggles TIOB. */
+/*@}*/
+
+/*! \name Counter Value Register */
+/*@{*/
+#define TC0_CV          (TC_BASE + 0x10)        /*!< \brief Counter 0 value. */
+#define TC1_CV          (TC_BASE + 0x50)        /*!< \brief Counter 1 value. */
+#define TC2_CV          (TC_BASE + 0x90)        /*!< \brief Counter 2 value. */
+/*@}*/
+
+/*! \name Timer Counter Register A */
+/*@{*/
+#define TC0_RA          (TC_BASE + 0x14)        /*!< \brief Channel 0 register A. */
+#define TC1_RA          (TC_BASE + 0x54)        /*!< \brief Channel 1 register A. */
+#define TC2_RA          (TC_BASE + 0x94)        /*!< \brief Channel 2 register A. */
+/*@}*/
+
+/*! \name Timer Counter Register B */
+/*@{*/
+#define TC0_RB          (TC_BASE + 0x18)        /*!< \brief Channel 0 register B. */
+#define TC1_RB          (TC_BASE + 0x58)        /*!< \brief Channel 1 register B. */
+#define TC2_RB          (TC_BASE + 0x98)        /*!< \brief Channel 2 register B. */
+/*@}*/
+
+/*! \name Timer Counter Register C */
+/*@{*/
+#define TC0_RC          (TC_BASE + 0x1C)        /*!< \brief Channel 0 register C. */
+#define TC1_RC          (TC_BASE + 0x5C)        /*!< \brief Channel 1 register C. */
+#define TC2_RC          (TC_BASE + 0x9C)        /*!< \brief Channel 2 register C. */
+/*@}*/
+
+
+/*! \name Timer Counter Status and Interrupt Registers */
+/*@{*/
+#define TC0_SR          (TC_BASE + 0x20)        /*!< \brief Status register address. */
+#define TC1_SR          (TC_BASE + 0x60)        /*!< \brief Status register address. */
+#define TC2_SR          (TC_BASE + 0xA0)        /*!< \brief Status register address. */
+
+#define TC0_IER         (TC_BASE + 0x24)        /*!< \brief Channel 0 interrupt enable register address. */
+#define TC1_IER         (TC_BASE + 0x64)        /*!< \brief Channel 1 interrupt enable register address. */
+#define TC2_IER         (TC_BASE + 0xA4)        /*!< \brief Channel 2 interrupt enable register address. */
+
+#define TC0_IDR         (TC_BASE + 0x28)        /*!< \brief Channel 0 interrupt disable register address. */
+#define TC1_IDR         (TC_BASE + 0x68)        /*!< \brief Channel 1 interrupt disable register address. */
+#define TC2_IDR         (TC_BASE + 0xA8)        /*!< \brief Channel 2 interrupt disable register address. */
+
+#define TC0_IMR         (TC_BASE + 0x2C)        /*!< \brief Channel 0 interrupt mask register address. */
+#define TC1_IMR         (TC_BASE + 0x6C)        /*!< \brief Channel 1 interrupt mask register address. */
+#define TC2_IMR         (TC_BASE + 0xAC)        /*!< \brief Channel 2 interrupt mask register address. */
+
+#define TC_COVFS                0x00000001      /*!< \brief Counter overflow flag. */
+#define TC_LOVRS                0x00000002      /*!< \brief Load overrun flag. */
+#define TC_CPAS                 0x00000004      /*!< \brief RA compare flag. */
+#define TC_CPBS                 0x00000008      /*!< \brief RB compare flag. */
+#define TC_CPCS                 0x00000010      /*!< \brief RC compare flag. */
+#define TC_LDRAS                0x00000020      /*!< \brief RA loading flag. */
+#define TC_LDRBS                0x00000040      /*!< \brief RB loading flag. */
+#define TC_ETRGS                0x00000080      /*!< \brief External trigger flag. */
+#define TC_CLKSTA               0x00010000      /*!< \brief Clock enable flag. */
+#define TC_MTIOA                0x00020000      /*!< \brief TIOA flag. */
+#define TC_MTIOB                0x00040000      /*!< \brief TIOB flag. */
+/*@}*/
+
+/*! \name Timer Counter Block Control Register */
+/*@{*/
+#define TC_BCR          (TC_BASE + 0xC0)        /*!< \brief Block control register address. */
+#define TC_SYNC                 0x00000001      /*!< \brief Synchronisation trigger */
+/*@}*/
+
+/*! \name Timer Counter Block Mode Register */
+/*@{*/
+#define TC_BMR          (TC_BASE + 0xC4)        /*!< \brief Block mode register address. */
+#define TC_TC0XC0S              0x00000003      /*!< \brief External clock signal 0 selection mask. */
+#define TC_TCLK0XC0             0x00000000      /*!< \brief Selects TCLK0. */
+#define TC_NONEXC0              0x00000001      /*!< \brief None selected. */
+#define TC_TIOA1XC0             0x00000002      /*!< \brief Selects TIOA1. */
+#define TC_TIOA2XC0             0x00000003      /*!< \brief Selects TIOA2. */
+
+#define TC_TC1XC1S              0x0000000C      /*!< \brief External clock signal 1 selection mask. */
+#define TC_TCLK1XC1             0x00000000      /*!< \brief Selects TCLK1. */
+#define TC_NONEXC1              0x00000004      /*!< \brief None selected. */
+#define TC_TIOA0XC1             0x00000008      /*!< \brief Selects TIOA0. */
+#define TC_TIOA2XC1             0x0000000C      /*!< \brief Selects TIOA2. */
+
+#define TC_TC2XC2S              0x00000030      /*!< \brief External clock signal 2 selection mask. */
+#define TC_TCLK2XC2             0x00000000      /*!< \brief Selects TCLK2. */
+#define TC_NONEXC2              0x00000010      /*!< \brief None selected. */
+#define TC_TIOA0XC2             0x00000020      /*!< \brief Selects TIOA0. */
+#define TC_TIOA1XC2             0x00000030      /*!< \brief Selects TIOA1. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Tc */
+
+#endif                          /* _ARCH_ARM_AT91_TC_H_ */

include/arch/arm/at91_twi.h

@@ -0,0 +1,151 @@
+#ifndef _ARCH_ARM_AT91_TWI_H_
+#define _ARCH_ARM_AT91_TWI_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_twi.h
+ * \brief AT91 two wire interface.
+ *
+ * \verbatim
+ *
+ * $Log: at91_twi.h,v $
+ * Revision 1.1  2006/08/31 19:19:55  haraldkipp
+ * No time to write comments. ;-)
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Twi
+ */
+/*@{*/
+
+/*! \name TWI Control Register */
+/*@{*/
+#define TWI_CR_OFF              0x00000000      /*!< \brief Control register offset. */
+#define TWI_CR      (TWI_BASE + TWI_CR_OFF)     /*!< \brief Control register address. */
+#define TWI_START               0x00000001      /*!< \brief Send start condition. */
+#define TWI_STOP                0x00000002      /*!< \brief Send stop condition. */
+#define TWI_MSEN                0x00000004      /*!< \brief Enable master mode. */
+#define TWI_MSDIS               0x00000008      /*!< \brief Disable master mode. */
+#define TWI_SVEN                0x00000010      /*!< \brief Enable slave mode. */
+#define TWI_SVDIS               0x00000020      /*!< \brief Disable slave mode. */
+#define TWI_SWRST               0x00000080      /*!< \brief Software reset. */
+/*@}*/
+
+/*! \name TWI Master Mode Register */
+/*@{*/
+#define TWI_MMR_OFF             0x00000004      /*!< \brief Master mode register offset. */
+#define TWI_MMR     (TWI_BASE + TWI_MMR_OFF)    /*!< \brief Master mode register address. */
+#define TWI_IADRSZ              0x00000300      /*!< \brief Internal device address size mask. */
+#define TWI_IADRSZ_NONE         0x00000000      /*!< \brief No internal device address. */
+#define TWI_IADRSZ_1BYTE        0x00000100      /*!< \brief One byte internal device address. */
+#define TWI_IADRSZ_2BYTE        0x00000200      /*!< \brief Two byte internal device address. */
+#define TWI_IADRSZ_3BYTE        0x00000300      /*!< \brief Three byte internal device address. */
+#define TWI_MREAD               0x00001000      /*!< \brief Master read direction. */
+#define TWI_DADR                0x007F0000      /*!< \brief Device address mask. */
+#define TWI_DADR_LSB                    16      /*!< \brief Device address LSB. */
+/*@}*/
+
+/*! \name TWI Slave Mode Register */
+/*@{*/
+#define TWI_SMR_OFF             0x00000008      /*!< \brief Slave mode register offset. */
+#define TWI_SMR     (TWI_BASE + TWI_SMR_OFF)    /*!< \brief Slave mode register address. */
+#define TWI_SADR                0x007F0000      /*!< \brief Slave address mask. */
+#define TWI_SADR_LSB                    16      /*!< \brief Slave address LSB. */
+/*@}*/
+
+/*! \name TWI Internal Address Register */
+/*@{*/
+#define TWI_IADRR_OFF           0x0000000C      /*!< \brief Internal address register offset. */
+#define TWI_IADRR   (TWI_BASE + TWI_IADRR_OFF)  /*!< \brief Internal address register address. */
+#define TWI_IADR                0x00FFFFFF      /*!< \brief Internal address mask. */
+#define TWI_IADR_LSB                    0       /*!< \brief Internal address LSB. */
+/*@}*/
+
+/*! \name TWI Clock Waveform Generator Register */
+/*@{*/
+#define TWI_CWGR_OFF            0x00000010      /*!< \brief Clock waveform generator register offset. */
+#define TWI_CWGR    (TWI_BASE + TWI_CWGR_OFF)   /*!< \brief Clock waveform generator register address. */
+#define TWI_CLDIV                0x000000FF     /*!< \brief Clock low divider mask. */
+#define TWI_CLDIV_LSB                    0      /*!< \brief Clock low divider LSB. */
+#define TWI_CHDIV                0x0000FF00     /*!< \brief Clock high divider mask. */
+#define TWI_CHDIV_LSB                    8      /*!< \brief Clock high divider LSB. */
+#define TWI_CKDIV                0x00070000     /*!< \brief Clock divider mask. */
+#define TWI_CKDIV_LSB                    16     /*!< \brief Clock divider LSB. */
+/*@}*/
+
+/*! \name TWI Status and Interrupt Registers */
+/*@{*/
+#define TWI_SR_OFF              0x00000020      /*!< \brief Status register offset. */
+#define TWI_SR      (TWI_BASE + TWI_SR_OFF)     /*!< \brief Status register address. */
+
+#define TWI_IER_OFF             0x00000024      /*!< \brief Interrupt enable register offset. */
+#define TWI_IER     (TWI_BASE + TWI_IER_OFF)    /*!< \brief Interrupt enable register address. */
+
+#define TWI_IDR_OFF             0x00000028      /*!< \brief Interrupt disable register offset. */
+#define TWI_IDR     (TWI_BASE + TWI_IDR_OFF)    /*!< \brief Interrupt disable register address. */
+
+#define TWI_IMR_OFF             0x0000002C      /*!< \brief Interrupt mask register offset. */
+#define TWI_IMR     (TWI_BASE + TWI_IMR_OFF)    /*!< \brief Interrupt mask register address. */
+
+#define TWI_TXCOMP              0x00000001      /*!< \brief Transmission completed. */
+#define TWI_RXRDY               0x00000002      /*!< \brief Receive holding register ready. */
+#define TWI_TXRDY               0x00000004      /*!< \brief Transmit holding register ready. */
+#define TWI_SVREAD              0x00000008      /*!< \brief Slave read. */
+#define TWI_SVACC               0x00000010      /*!< \brief Slave access. */
+#define TWI_GACC                0x00000020      /*!< \brief General call access. */
+#define TWI_OVRE                0x00000040      /*!< \brief Overrun error. */
+#define TWI_NACK                0x00000100      /*!< \brief Not acknowledged. */
+#define TWI_ARBLST              0x00000200      /*!< \brief Arbitration lost. */
+#define TWI_SCLWS               0x00000400      /*!< \brief Clock wait state. */
+#define TWI_EOSACC              0x00000800      /*!< \brief End of slave access. */
+/*@}*/
+
+/*! \name TWI Receive Holding Register */
+/*@{*/
+#define TWI_RHR_OFF             0x00000030      /*!< \brief Receive holding register offset. */
+#define TWI_RHR     (TWI_BASE + TWI_RHR_OFF)    /*!< \brief Receive holding register address. */
+/*@}*/
+
+/*! \name TWI Transmit Holding Register */
+/*@{*/
+#define TWI_THR_OFF             0x00000034      /*!< \brief Transmit holding register offset. */
+#define TWI_THR     (TWI_BASE + TWI_THR_OFF)    /*!< \brief Transmit holding register address. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Twi */
+
+#endif                          /* _ARCH_ARM_AT91_TWI_H_ */

include/arch/arm/at91_us.h

@@ -0,0 +1,270 @@
+#ifndef _ARCH_ARM_AT91_US_H_
+#define _ARCH_ARM_AT91_US_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_us.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_us.h,v $
+ * Revision 1.3  2006/08/31 19:12:43  haraldkipp
+ * Added additional registers found on the AT91SAM9260.
+ *
+ * Revision 1.2  2006/08/05 11:55:30  haraldkipp
+ * PDC registers are now configurable in the parent header file.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Us
+ */
+/*@{*/
+
+/*! \name USART Control Register */
+/*@{*/
+#define US_CR_OFF               0x00000000      /*!< \brief USART control register offset. */
+#define US0_CR  (USART0_BASE + US_CR_OFF)       /*!< \brief Channel 0 control register address. */
+#define US1_CR  (USART1_BASE + US_CR_OFF)       /*!< \brief Channel 1 control register address. */
+#define US_RSTRX                0x00000004      /*!< \brief Reset receiver */
+#define US_RSTTX                0x00000008      /*!< \brief Reset transmitter */
+#define US_RXEN                 0x00000010      /*!< \brief Receiver enable */
+#define US_RXDIS                0x00000020      /*!< \brief Receiver disable */
+#define US_TXEN                 0x00000040      /*!< \brief Transmitter enable */
+#define US_TXDIS                0x00000080      /*!< \brief Transmitter disable */
+#define US_RSTSTA               0x00000100      /*!< \brief Reset status bits */
+#define US_STTBRK               0x00000200      /*!< \brief Start break */
+#define US_STPBRK               0x00000400      /*!< \brief Stop break */
+#define US_STTTO                0x00000800      /*!< \brief Start timeout */
+#define US_SENDA                0x00001000      /*!< \brief Send next byte with address bit set. */
+/*@}*/
+
+/*! \name Mode Register */
+/*@{*/
+#define US_MR_OFF               0x00000004      /*!< \brief USART mode register offset. */
+#define US0_MR  (USART0_BASE + US_MR_OFF)       /*!< \brief Channel 0 mode register address. */
+#define US1_MR  (USART1_BASE + US_MR_OFF)       /*!< \brief Channel 1 mode register address. */
+
+#define US_CLKS                 0x00000030      /*!< \brief Clock selection mask. */
+#define US_CLKS_MCK             0x00000000      /*!< \brief Master clock. */
+#define US_CLKS_MCK8            0x00000010      /*!< \brief Master clock divided by 8. */
+#define US_CLKS_SCK             0x00000020      /*!< \brief External clock. */
+#define US_CLKS_SLCK            0x00000030      /*!< \brief Slow clock. */
+
+#define US_CHRL                 0x000000C0      /*!< \brief Masks data length. */
+#define US_CHRL_5               0x00000000      /*!< \brief 5 data bits. */
+#define US_CHRL_6               0x00000040      /*!< \brief 6 data bits. */
+#define US_CHRL_7               0x00000080      /*!< \brief 7 data bits. */
+#define US_CHRL_8               0x000000C0      /*!< \brief 8 data bits. */
+
+#define US_SYNC                 0x00000100      /*!< \brief Synchronous mode enable. */
+
+#define US_PAR                  0x00000E00      /*!< \brief Parity mode mask. */
+#define US_PAR_EVEN             0x00000000      /*!< \brief Even parity */
+#define US_PAR_ODD              0x00000200      /*!< \brief Odd parity */
+#define US_PAR_SPACE            0x00000400      /*!< \brief Space parity. */
+#define US_PAR_MARK             0x00000600      /*!< \brief Marked parity. */
+#define US_PAR_NO               0x00000800      /*!< \brief No parity. */
+#define US_PAR_MULTIDROP        0x00000C00      /*!< \brief Multi-drop mode. */
+
+#define US_NBSTOP               0x00003000      /*!< \brief Masks stop bit length. */
+#define US_NBSTOP_1             0x00000000      /*!< \brief 1 stop bit. */
+#define US_NBSTOP_1_5           0x00001000      /*!< \brief 1.5 stop bits. */
+#define US_NBSTOP_2             0x00002000      /*!< \brief 2 stop bits. */
+
+#define US_CHMODE                   0x0000C000  /*!< \brief Channel mode mask. */
+#define US_CHMODE_NORMAL            0x00000000  /*!< \brief Normal mode. */
+#define US_CHMODE_AUTOMATIC_ECHO    0x00004000  /*!< \brief Automatic echo. */
+#define US_CHMODE_LOCAL_LOOPBACK    0x00008000  /*!< \brief Local loopback. */
+#define US_CHMODE_REMOTE_LOOPBACK   0x0000C000  /*!< \brief Remote loopback. */
+
+#define US_MODE9                0x00020000      /*!< \brief 9 bit mode. */
+
+#define US_CLKO                 0x00040000      /*!< \brief Baud rate output enable */
+/*@}*/
+
+/*! \name Status and Interrupt Register */
+/*@{*/
+#define US_CSR_OFF              0x00000014      /*!< \brief USART status register offset. */
+#define US0_CSR (USART0_BASE + US_CSR_OFF)      /*!< \brief Channel 0 status register address. */
+#define US1_CSR (USART1_BASE + US_CSR_OFF)      /*!< \brief Channel 1 status register address. */
+
+#define US_IER_OFF              0x00000008      /*!< \brief USART interrupt enable register offset. */
+#define US0_IER (USART0_BASE + US_IER_OFF)      /*!< \brief Channel 0 interrupt enable register address. */
+#define US1_IER (USART1_BASE + US_IER_OFF)      /*!< \brief Channel 1 interrupt enable register address. */
+
+#define US_IDR_OFF              0x0000000C      /*!< \brief USART interrupt disable register offset. */
+#define US0_IDR (USART0_BASE + US_IDR_OFF)      /*!< \brief Channel 0 interrupt disable register address. */
+#define US1_IDR (USART1_BASE + US_IDR_OFF)      /*!< \brief Channel 1 interrupt disable register address. */
+
+#define US_IMR_OFF              0x00000010      /*!< \brief USART interrupt mask register offset. */
+#define US0_IMR (USART0_BASE + US_IMR_OFF)      /*!< \brief Channel 0 interrupt mask register address. */
+#define US1_IMR (USART1_BASE + US_IMR_OFF)      /*!< \brief Channel 1 interrupt mask register address. */
+
+#define US_RXRDY                0x00000001      /*!< \brief Receiver ready */
+#define US_TXRDY                0x00000002      /*!< \brief Transmitter ready */
+#define US_RXBRK                0x00000004      /*!< \brief Receiver break */
+#define US_ENDRX                0x00000008      /*!< \brief End of receiver PDC transfer */
+#define US_ENDTX                0x00000010      /*!< \brief End of transmitter PDC transfer */
+#define US_OVRE                 0x00000020      /*!< \brief Overrun error */
+#define US_FRAME                0x00000040      /*!< \brief Framing error */
+#define US_PARE                 0x00000080      /*!< \brief Parity error */
+#define US_TIMEOUT              0x00000100      /*!< \brief Receiver timeout */
+#define US_TXEMPTY              0x00000200      /*!< \brief Transmitter empty */
+
+/*! \brief Baud rate calculation helper macro. 
+ *
+ * \deprecated Use NutGetCpuClock() and calculate the divider value locally.
+ */
+#define AT91_US_BAUD(baud) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
+/*@}*/
+
+/*! \name Receiver Holding Register */
+/*@{*/
+#define US_RHR_OFF              0x00000018      /*!< \brief USART receiver holding register offset. */
+#define US0_RHR (USART0_BASE + US_RHR_OFF)      /*!< \brief Channel 0 receiver holding register address. */
+#define US1_RHR (USART1_BASE + US_RHR_OFF)      /*!< \brief Channel 1 receiver holding register address. */
+/*@}*/
+
+/*! \name Transmitter Holding Register */
+/*@{*/
+#define US_THR_OFF              0x0000001C      /*!< \brief USART transmitter holding register offset. */
+#define US0_THR (USART0_BASE + US_THR_OFF)      /*!< \brief Channel 0 transmitter holding register address. */
+#define US1_THR (USART1_BASE + US_THR_OFF)      /*!< \brief Channel 1 transmitter holding register address. */
+/*@}*/
+
+/*! \name Baud Rate Generator Register */
+/*@{*/
+#define US_BRGR_OFF             0x00000020      /*!< \brief USART baud rate register offset. */
+#define US0_BRGR (USART0_BASE + US_BRGR_OFF)    /*!< \brief Channel 0 baud rate register address. */
+#define US1_BRGR (USART1_BASE + US_BRGR_OFF)    /*!< \brief Channel 1 baud rate register address. */
+/*@}*/
+
+/*! \name Receiver Timeout Register */
+/*@{*/
+#define US_RTOR_OFF             0x00000024      /*!< \brief USART receiver timeout register offset. */
+#define US0_RTOR (USART0_BASE + US_RTOR_OFF)    /*!< \brief Channel 0 receiver timeout register address. */
+#define US1_RTOR (USART1_BASE + US_RTOR_OFF)    /*!< \brief Channel 1 receiver timeout register address. */
+/*@}*/
+
+/*! \name Transmitter Time Guard Register */
+/*@{*/
+#define US_TTGR_OFF             0x00000028      /*!< \brief USART transmitter time guard register offset. */
+#define US0_TTGR (USART0_BASE + US_TTGR_OFF)    /*!< \brief Channel 0 transmitter time guard register address. */
+#define US1_TTGR (USART1_BASE + US_TTGR_OFF)    /*!< \brief Channel 1 transmitter time guard register address. */
+/*@}*/
+
+/*! \name FI DI Ratio Register */
+/*@{*/
+#define US_FIDI_OFF             0x00000040      /*!< \brief USART FI DI ratio register offset. */
+#define US0_FIDI (USART0_BASE + US_FIDI_OFF)    /*!< \brief Channel 0 FI DI ratio register address. */
+#define US1_FIDI (USART1_BASE + US_FIDI_OFF)    /*!< \brief Channel 1 FI DI ratio register address. */
+/*@}*/
+
+/*! \name Error Counter Register */
+/*@{*/
+#define US_NER_OFF              0x00000044      /*!< \brief USART error counter register offset. */
+#define US0_NER  (USART0_BASE + US_NER_OFF)     /*!< \brief Channel 0 error counter register address. */
+#define US1_NER  (USART1_BASE + US_NER_OFF)     /*!< \brief Channel 1 error counter register address. */
+/*@}*/
+
+/*! \name IrDA Filter Register */
+/*@{*/
+#define US_IF_OFF               0x0000004C      /*!< \brief USART IrDA filter register offset. */
+#define US0_IF (USART0_BASE + US_IF_OFF)        /*!< \brief Channel 0 IrDA filter register address. */
+#define US1_IF (USART1_BASE + US_IF_OFF)        /*!< \brief Channel 1 IrDA filter register address. */
+/*@}*/
+
+#if defined(USART_HAS_PDC)
+
+/*! \name Receive Pointer Register */
+/*@{*/
+#define US0_RPR (USART0_BASE + PERIPH_RPR_OFF)      /*!< \brief Channel 0 receive pointer register address. */
+#define US1_RPR (USART1_BASE + PERIPH_RPR_OFF)      /*!< \brief Channel 1 receive pointer register address. */
+/*@}*/
+
+/*! \name Receive Counter Register */
+/*@{*/
+#define US0_RCR (USART0_BASE + PERIPH_RCR_OFF)      /*!< \brief Channel 0 receive counter register address. */
+#define US1_RCR (USART1_BASE + PERIPH_RCR_OFF)      /*!< \brief Channel 1 receive counter register address. */
+/*@}*/
+
+/*! \name Transmit Pointer Register */
+/*@{*/
+#define US0_TPR (USART0_BASE + PERIPH_TPR_OFF)      /*!< \brief Channel 0 transmit pointer register address. */
+#define US1_TPR (USART1_BASE + PERIPH_TPR_OFF)      /*!< \brief Channel 1 transmit pointer register address. */
+/*@}*/
+
+/*! \name Transmit Counter Register */
+/*@{*/
+#define US0_TCR (USART0_BASE + PERIPH_TCR_OFF)      /*!< \brief Channel 0 transmit counter register address. */
+#define US1_TCR (USART1_BASE + PERIPH_TCR_OFF)      /*!< \brief Channel 1 transmit counter register address. */
+/*@}*/
+
+#if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
+#define US0_RNPR   (USART0_BASE + PERIPH_RNPR_OFF)  /*!< \brief PDC channel 0 receive next pointer register. */
+#define US1_RNPR   (USART1_BASE + PERIPH_RNPR_OFF)  /*!< \brief PDC channel 1 receive next pointer register. */
+#define US0_RNCR   (USART0_BASE + PERIPH_RNCR_OFF)  /*!< \brief PDC channel 0 receive next counter register. */
+#define US1_RNCR   (USART1_BASE + PERIPH_RNCR_OFF)  /*!< \brief PDC channel 1 receive next counter register. */
+#endif
+
+#if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
+#define US0_TNPR   (USART0_BASE + PERIPH_TNPR_OFF)  /*!< \brief PDC channel 0 transmit next pointer register. */
+#define US1_TNPR   (USART1_BASE + PERIPH_TNPR_OFF)  /*!< \brief PDC channel 1 transmit next pointer register. */
+#define US0_TNCR   (USART0_BASE + PERIPH_TNCR_OFF)  /*!< \brief PDC channel 0 transmit next counter register. */
+#define US1_TNCR   (USART1_BASE + PERIPH_TNCR_OFF)  /*!< \brief PDC channel 1 transmit next counter register. */
+#endif
+
+#if defined(PERIPH_PTCR_OFF)
+#define US0_PTCR   (USART0_BASE + PERIPH_PTCR_OFF)  /*!< \brief PDC channel 0 transfer control register. */
+#define US1_PTCR   (USART1_BASE + PERIPH_PTCR_OFF)  /*!< \brief PDC channel 1 transfer control register. */
+#endif
+
+#if defined(PERIPH_PTSR_OFF)
+#define US0_PTSR   (USART0_BASE + PERIPH_PTSR_OFF)  /*!< \brief PDC channel 0 transfer status register. */
+#define US1_PTSR   (USART1_BASE + PERIPH_PTSR_OFF)  /*!< \brief PDC channel 1 transfer status register. */
+#endif
+
+#endif  /* USART_HAS_PDC */
+
+/*@} xgNutArchArmAt91Us */
+
+
+#endif                          /* _ARCH_ARM_AT91_US_H_ */

include/arch/arm/at91_wd.h

@@ -0,0 +1,92 @@
+#ifndef _ARCH_ARM_AT91_WD_H_
+#define _ARCH_ARM_AT91_WD_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_wd.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_wd.h,v $
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Wd
+ */
+/*@{*/
+
+/*! \name Watch Dog Overflow Mode Register */
+/*@{*/
+#define WD_OMR          (WD_BASE + 0x00)        /*!< \brief Overflow mode register address. */
+#define WD_WDEN                 0x00000001      /*!< \brief Watch Dog enable. */
+#define WD_RSTEN                0x00000002      /*!< \brief Internal reset enable. */
+#define WD_IRQEN                0x00000004      /*!< \brief Interrupt enable. */
+#define WD_EXTEN                0x00000008      /*!< \brief External signal enable. */
+#define WD_OKEY                 0x00002340      /*!< \brief Overflow mode register access key. */
+/*@}*/
+
+/*! \name Watch Dog Clock Register */
+/*@{*/
+#define WD_CMR          (WD_BASE + 0x04)        /*!< \brief Clock mode register address. */
+#define WD_WDCLKS               0x00000003      /*!< \brief Clock selection mask. */
+#define WD_WDCLKS_MCK8          0x00000000      /*!< \brief Selects MCK/8. */
+#define WD_WDCLKS_MCK32         0x00000001      /*!< \brief Selects MCK/32. */
+#define WD_WDCLKS_MCK128        0x00000002      /*!< \brief Selects MCK/128. */
+#define WD_WDCLKS_MCK1024       0x00000003      /*!< \brief Selects MCK/1024. */
+#define WD_HPCV                 0x0000003C      /*!< \brief High preload counter value. */
+#define WD_CKEY                 (0x06E<<7)      /*!< \brief Clock register access key. */
+/*@}*/
+
+/*! \name Watch Dog Control Register */
+/*@{*/
+#define WD_CR           (WD_BASE + 0x08)        /*!< \brief Control register address. */
+#define WD_RSTKEY               0x0000C071      /*!< \brief Watch Dog restart key. */
+/*@}*/
+
+/*! \name Watch Dog Status Register */
+/*@{*/
+#define WD_SR           (WD_BASE + 0x0C)        /*!< \brief Status register address. */
+#define WD_WDOVF                0x00000001      /*!< \brief Watch Dog overflow status. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Wd */
+
+#endif                          /* _ARCH_ARM_AT91_WD_H_ */
+

include/arch/arm/at91_wdt.h

@@ -0,0 +1,98 @@
+#ifndef _ARCH_ARM_AT91_WDT_H_
+#define _ARCH_ARM_AT91_WDT_H_
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91_wdt.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91_wdt.h,v $
+ * Revision 1.3  2006/08/31 19:13:44  haraldkipp
+ * Added LSB definitions for counter and delta values.
+ *
+ * Revision 1.2  2006/07/18 14:06:18  haraldkipp
+ * Changed coding style to follow existing headers.
+ * Removed old lines, which had been derived from at91_wd.h.
+ * Corrected register addresses, thanks to Jix.
+ * Register names changed, now following the datasheet.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ *
+ * \endverbatim
+ */
+
+/*!
+ * \addtogroup xgNutArchArmAt91Wdt
+ */
+/*@{*/
+
+/*! \name Watch Dog Control Register */
+/*@{*/
+#define WDT_CR_OFF          0x00000000  /*!< \brief Watchdog control register offset. */
+#define WDT_CR  (WDT_BASE + WDT_CR_OFF) /*!< \brief Watchdog control register address. */
+#define WDT_WDRSTT          0x00000001  /*!< \brief Watchdog restart. */
+#define WDT_KEY             0xA5000000  /*!< \brief Watchdog password. */
+/*@}*/
+
+/*! \name Watch Dog Mode Register */
+/*@{*/
+#define WDT_MR_OFF          0x00000004  /*!< \brief Mode register offset. */
+#define WDT_MR  (WDT_BASE + WDT_MR_OFF) /*!< \brief Mode register address. */
+#define WDT_WDV             0x00000FFF  /*!< \brief Counter value mask. */
+#define WDT_WDV_LSB                 0   /*!< \brief Counter value LSB. */
+#define WDT_WDFIEN          0x00001000  /*!< \brief Fault interrupt enable. */
+#define WDT_WDRSTEN         0x00002000  /*!< \brief Reset enable. */
+#define WDT_WDRPROC         0x00004000  /*!< \brief Eset processor enable. */
+#define WDT_WDDIS           0x00008000  /*!< \brief Watchdog disable. */
+#define WDT_WDD             0x0FFF0000  /*!< \brief Delta value mask. */
+#define WDT_WDD_LSB                 16  /*!< \brief Delta value LSB. */
+#define WDT_WDDBGHLT        0x10000000  /*!< \brief Watchdog debug halt. */
+#define WDT_WDIDLEHLT       0x20000000  /*!< \brief Watchdog idle halt. */
+/*@}*/
+
+/*! \name Watch Dog Status Register */
+/*@{*/
+#define WDT_SR_OFF          0x00000008  /*!< \brief Status register offset. */
+#define WDT_SR  (WDT_BASE + WDT_SR_OFF) /*!< \brief Status register address. */
+#define WDT_WDUNF           0x00000001  /*!< \brief Watchdog underflow. */
+#define WDT_WDERR           0x00000002  /*!< \brief Watchdog error. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Wdt */
+
+#endif                          /* _ARCH_ARM_AT91_WDT_H_ */

include/arch/arm/at91eb40a.h

@@ -0,0 +1,67 @@
+#define FLASH_BASE      ((u_int *)0x01000000)
+#define FLASH_SIZE      (2*1024*1024)
+
+/* 
+ * EBI initialization.
+ *
+ * 0x01000000, 16MB, 2 tdf, 16 bits, 7 WS  
+ */
+#define EBI_CSR_0       ((u_int *)(FLASH_BASE | 0x2539)     
+#define EBI_CSR_1       ((u_int *)0x10000000)
+#define EBI_CSR_2       ((u_int *)0x20000000)
+#define EBI_CSR_3       ((u_int *)0x30000000)
+#define EBI_CSR_4       ((u_int *)0x40000000)
+#define EBI_CSR_5       ((u_int *)0x50000000)
+#define EBI_CSR_6       ((u_int *)0x60000000)
+#define EBI_CSR_7       ((u_int *)0x70000000)
+
+/*
+ * LEDs
+ */
+#define LED1            _BV(16)
+#define LED2            _BV(17)
+#define LED3            _BV(18)
+#define LED4            _BV(19)
+#define LED5            _BV(3)
+#define LED6            _BV(4)
+#define LED7            _BV(5)
+#define LED8            _BV(6)
+
+#define LED_PIO_CTRL    1
+#define LED_MASK        (LED1|LED2|LED3|LED4|LED5|LED6|LED7|LED8)
+
+#define LED_ON          PIO_CLEAR_OUT
+#define LED_OFF         PIO_SET_OUT
+
+#define SW1_MASK        _BV(12)
+#define SW2_MASK        _BV(9)
+#define SW3_MASK        _BV(1)
+#define SW4_MASK        _BV(2)
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+/*
+ * Push buttons.
+ */
+#define SW1             _BV(12)
+#define SW2             _BV(9)
+#define SW3             _BV(1)
+#define SW4             _BV(2)
+
+#define PIO_SW1         _BV(12)
+#define PIO_SW2         _BV(9)
+#define PIO_SW3         _BV(1)
+#define PIO_SW4         _BV(2)
+
+/*
+ * Serial EEPROM
+ */
+#define SCL             _BV(8)
+#define SDA             _BV(7)
+#define PIO_SCL         _BV(8)
+#define PIO_SDA         _BV(7)
+
+/*
+ * Master clock.
+ */
+#define MCK             66000000
+#define MCKKHz          (MCK/1000)

include/arch/arm/at91sam7x.h

@@ -0,0 +1,405 @@
+#ifndef _ARCH_ARM_SAM7X_H_
+#define _ARCH_ARM_SAM7X_H_
+/*
+ * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * Change to sam7x.h
+ *     By HU Daoxu, 2006/05/26
+ *
+ * \file arch/arm/at91sam7x.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91sam7x.h,v $
+ * Revision 1.8  2007/02/15 16:11:14  haraldkipp
+ * Support for system controller interrupts added.
+ *
+ * Revision 1.7  2006/10/08 16:48:09  haraldkipp
+ * Documentation fixed
+ *
+ * Revision 1.6  2006/09/29 12:45:08  haraldkipp
+ * Added PIO features and SPI peripheral selections.
+ *
+ * Revision 1.5  2006/09/07 09:09:06  haraldkipp
+ * Added missing definitions for peripheral multiplexing. Now following the
+ * same naming conventions like those for the SAM9260.
+ *
+ * Revision 1.4  2006/08/05 11:57:38  haraldkipp
+ * PDC register configuration added.
+ * Added register definitions for synchronous serial controller.
+ *
+ * Revision 1.3  2006/07/21 09:03:56  haraldkipp
+ * Added SPI support, kindly contributed by Andras Albert.
+ *
+ * Revision 1.2  2006/07/15 11:14:45  haraldkipp
+ * Missing base addresses and peripheral IDs added.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * Revision 1.3  2006/01/05 16:52:49  haraldkipp
+ * Baudrate calculation is now based on NutGetCpuClock().
+ * The AT91_US_BAUD macro had been marked deprecated.
+ *
+ * Revision 1.2  2005/11/20 14:44:14  haraldkipp
+ * Register offsets added.
+ *
+ * Revision 1.1  2005/10/24 10:31:13  haraldkipp
+ * Moved from parent directory.
+ *
+ *
+ * \endverbatim
+ */
+
+#define FLASH_BASE      0x100000UL
+#define RAM_BASE        0x200000UL
+
+#define TC_BASE         0xFFFA0000      /*!< \brief Timer/counter base address. */
+#define UDP_BASE        0xFFFB0000      /*!< \brief USB device port base address. */
+#define TWI_BASE        0xFFFB8000      /*!< \brief Two-wire interface base address. */
+#define USART0_BASE     0xFFFC0000      /*!< \brief USART 0 base address. */
+#define USART1_BASE     0xFFFC4000      /*!< \brief USART 1 base address. */
+#define PWMC_BASE       0xFFFCC000      /*!< \brief PWM controller base address. */
+#define CAN_BASE        0xFFFD0000      /*!< \brief CAN controller base address. */
+#define SSC_BASE        0xFFFD4000      /*!< \brief Serial synchronous controller base address. */
+#define ADC_BASE        0xFFFD8000      /*!< \brief ADC base address. */
+#define EMAC_BASE       0xFFFDC000      /*!< \brief EMAC base address. */
+#define SPI0_BASE       0xFFFE0000      /*!< \brief SPI0 base address. */
+#define SPI1_BASE       0xFFFE4000      /*!< \brief SPI0 base address. */
+
+#define AIC_BASE        0xFFFFF000      /*!< \brief AIC base address. */
+#define DBGU_BASE       0xFFFFF200      /*!< \brief DBGU base address. */
+#define PIOA_BASE       0xFFFFF400      /*!< \brief PIO A base address. */
+#define PIOB_BASE       0xFFFFF600      /*!< \brief PIO B base address. */
+#define PMC_BASE        0xFFFFFC00      /*!< \brief PMC base address. */
+#define RSTC_BASE       0xFFFFFD00      /*!< \brief Resect controller register base address. */
+#define RTT_BASE        0xFFFFFD20      /*!< \brief Realtime timer base address. */
+#define PIT_BASE        0xFFFFFD30      /*!< \brief Periodic interval timer base address. */
+#define WDT_BASE        0xFFFFFD40      /*!< \brief Watch Dog register base address. */
+#define VREG_BASE       0xFFFFFD60      /*!< \brief Voltage regulator mode controller base address. */
+#define MC_BASE         0xFFFFFF00      /*!< \brief Memory controller base. */
+
+#define PERIPH_RPR_OFF  0x00000100      /*!< \brief Receive pointer register offset. */
+#define PERIPH_RCR_OFF  0x00000104      /*!< \brief Receive counter register offset. */
+#define PERIPH_TPR_OFF  0x00000108      /*!< \brief Transmit pointer register offset. */
+#define PERIPH_TCR_OFF  0x0000010C      /*!< \brief Transmit counter register offset. */
+#define PERIPH_RNPR_OFF 0x00000110      /*!< \brief Receive next pointer register offset. */
+#define PERIPH_RNCR_OFF 0x00000114      /*!< \brief Receive next counter register offset. */
+#define PERIPH_TNPR_OFF 0x00000118      /*!< \brief Transmit next pointer register offset. */
+#define PERIPH_TNCR_OFF 0x0000011C      /*!< \brief Transmit next counter register offset. */
+#define PERIPH_PTCR_OFF 0x00000120      /*!< \brief PDC transfer control register offset. */
+#define PERIPH_PTSR_OFF 0x00000124      /*!< \brief PDC transfer status register offset. */
+
+#define PDC_RXTEN       0x00000001      /*!< \brief Receiver transfer enable. */
+#define PDC_RXTDIS      0x00000002      /*!< \brief Receiver transfer disable. */
+#define PDC_TXTEN       0x00000100      /*!< \brief Transmitter transfer enable. */
+#define PDC_TXTDIS      0x00000200      /*!< \brief Transmitter transfer disable. */
+
+#define DBGU_HAS_PDC
+#define SPI_HAS_PDC
+#define SSC_HAS_PDC
+#define USART_HAS_PDC
+
+#define PIO_HAS_MULTIDRIVER
+#define PIO_HAS_PULLUP
+#define PIO_HAS_PERIPHERALSELECT
+#define PIO_HAS_OUTPUTWRITEENABLE
+
+#include <arch/arm/at91_tc.h>
+#include <arch/arm/at91_us.h>
+#include <arch/arm/at91_dbgu.h>
+#include <arch/arm/at91_emac.h>
+#include <arch/arm/at91_spi.h>
+#include <arch/arm/at91_aic.h>
+#include <arch/arm/at91_pio.h>
+#include <arch/arm/at91_pmc.h>
+#include <arch/arm/at91_rstc.h>
+#include <arch/arm/at91_wdt.h>
+#include <arch/arm/at91_pit.h>
+#include <arch/arm/at91_mc.h>
+#include <arch/arm/at91_ssc.h>
+
+/*! \addtogroup xgNutArchArmAt91Sam7x */
+/*@{*/
+
+/*! \name Peripheral Identifiers and Interrupts */
+/*@{*/
+#define FIQ_ID      0       /*!< \brief Fast interrupt ID. */
+#define SYSC_ID     1       /*!< \brief System controller interrupt. */
+#define PIOA_ID     2       /*!< \brief Parallel I/O controller ID. */
+#define PIOB_ID     3       /*!< \brief Parallel I/O controller ID. */
+#define SPI0_ID     4       /*!< \brief Serial peripheral interface 0 ID. */
+#define SPI1_ID     5       /*!< \brief Serial peripheral interface 1 ID. */
+#define US0_ID      6       /*!< \brief USART 0 ID. */
+#define US1_ID      7       /*!< \brief USART 1 ID. */
+#define SSC_ID      8       /*!< \brief Synchronous serial controller ID. */
+#define TWI_ID      9       /*!< \brief Two-wire interface ID. */
+#define PWMC_ID     10      /*!< \brief PWM controller ID. */
+#define UDP_ID      11      /*!< \brief USB device port ID. */
+#define TC0_ID      12      /*!< \brief Timer 0 ID. */
+#define TC1_ID      13      /*!< \brief Timer 1 ID. */
+#define TC2_ID      14      /*!< \brief Timer 2 ID. */
+#define CAN_ID      15      /*!< \brief CAN controller ID. */
+#define EMAC_ID     16      /*!< \brief Ethernet MAC ID. */
+#define ADC_ID      17      /*!< \brief Analog to digital converter ID. */
+#define IRQ0_ID     30      /*!< \brief External interrupt 0 ID. */
+#define IRQ1_ID     31      /*!< \brief External interrupt 1 ID. */
+/*@}*/
+
+/*! \name Historical SPI0 Peripheral Multiplexing Names */
+/*@{*/
+#define SPI0_NPCS0_PA12A	12	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_NPCS1_PA13A	13	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_NPCS1_PA07B	7	/*!< \brief Port bit number on PIO-A Perpheral B. */
+#define SPI0_NPCS1_PB13B	13	/*!< \brief Port bit number on PIO-B Perpheral B. */
+#define SPI0_NPCS2_PA14A	14	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_NPCS2_PA08B	8	/*!< \brief Port bit number on PIO-A Perpheral B. */
+#define SPI0_NPCS2_PB14B	14	/*!< \brief Port bit number on PIO-B Perpheral B. */
+#define SPI0_NPCS3_PA15A	15	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_NPCS3_PA09B	9	/*!< \brief Port bit number on PIO-A Perpheral B. */
+#define SPI0_NPCS3_PB17B	17	/*!< \brief Port bit number on PIO-B Perpheral B. */
+#define SPI0_MISO_PA16A		16	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_MOSI_PA17A		17	/*!< \brief Port bit number on PIO-A Perpheral A. */
+#define SPI0_SPCK_PA18A		18	/*!< \brief Port bit number on PIO-A Perpheral A. */
+/*@}*/
+
+/*! \name USART Peripheral Multiplexing */
+/*@{*/
+#define PA0_RXD0_A          0
+#define PA1_TXD0_A          1
+#define PA2_SCK0_A          2
+#define PA3_RTS0_A          3
+#define PA4_CTS0_A          4
+
+#define PA5_RXD1_A          5
+#define PA6_TXD1_A          6
+#define PA7_SCK1_A          7
+#define PA8_RTS1_A          8
+#define PA9_CTS1_A          9
+#define PB23_DCD1_B         23
+#define PB24_DSR1_B         24
+#define PB25_DTR1_B         25
+#define PB26_RI1_B          26
+/*@}*/
+
+/*! \name SPI Peripheral Multiplexing */
+/*@{*/
+#define PA16_SPI0_MISO_A    16
+#define PA17_SPI0_MOSI_A    17
+#define PA18_SPI0_SPCK_A    18
+#define PA12_SPI0_NPCS0_A   12
+#define PA13_SPI0_NPCS1_A   13
+#define PA7_SPI0_NPCS1_B    7
+#define PA14_SPI0_NPCS2_A   14
+#define PB14_SPI0_NPCS2_B   14
+#define PA8_SPI0_NPCS2_B    8
+#define PA15_SPI0_NPCS3_A   15
+#define PA9_SPI0_NPCS3_B    9
+
+#define SPI0_PINS           _BV(PA16_SPI0_MISO_A) | _BV(PA17_SPI0_MOSI_A) | _BV(PA18_SPI0_SPCK_A)
+#define SPI0_PIO_BASE       PIOA_BASE
+#define SPI0_PSR_OFF        PIO_ASR_OFF
+
+#define SPI0_CS0_PIN        _BV(PA12_SPI0_NPCS0_A)
+#define SPI0_CS0_PIO_BASE   PIOA_BASE
+#define SPI0_CS0_PSR_OFF    PIO_ASR_OFF
+
+#ifndef SPI0_CS1_PIN
+#define SPI0_CS1_PIN        _BV(PA13_SPI0_NPCS1_A)
+#define SPI0_CS1_PIO_BASE   PIOA_BASE
+#define SPI0_CS1_PSR_OFF    PIO_ASR_OFF
+#endif
+
+#ifndef SPI0_CS2_PIN
+#define SPI0_CS2_PIN        _BV(PA14_SPI0_NPCS2_A)
+#define SPI0_CS2_PIO_BASE   PIOA_BASE
+#define SPI0_CS2_PSR_OFF    PIO_ASR_OFF
+#endif
+
+#ifndef SPI0_CS3_PIN
+#define SPI0_CS3_PIN        _BV(PA15_SPI0_NPCS3_A)
+#define SPI0_CS3_PIO_BASE   PIOA_BASE
+#define SPI0_CS3_PSR_OFF    PIO_ASR_OFF
+#endif
+
+#define PA24_SPI1_MISO_B    24
+#define PA23_SPI1_MOSI_B    23
+#define PA22_SPI1_SPCK_B    22
+#define PA21_SPI1_NPCS0_B   21
+#define PA25_SPI1_NPCS1_B   25
+#define PB13_SPI0_NPCS1_B   13
+#define PA2_SPI1_NPCS1_B    2
+#define PB10_SPI1_NPCS1_B   10
+#define PA26_SPI1_NPCS2_B   26
+#define PA3_SPI1_NPCS2_B    3
+#define PB11_SPI1_NPCS2_B   11
+#define PB17_SPI0_NPCS3_B   17
+#define PA4_SPI1_NPCS3_B    4
+#define PA29_SPI1_NPCS3_B   29
+#define PB16_SPI1_NPCS3_B   16
+
+#define SPI1_PINS           _BV(PA24_SPI1_MISO_B) | _BV(PA23_SPI1_MOSI_B) | _BV(PA22_SPI1_SPCK_B)
+#define SPI1_PIO_BASE       PIOA_BASE
+#define SPI1_PSR_OFF        PIO_BSR_OFF
+
+#define SPI1_CS0_PIN        _BV(PA21_SPI1_NPCS0_B)
+#define SPI1_CS0_PIO_BASE   PIOA_BASE
+#define SPI1_CS0_PSR_OFF    PIO_BSR_OFF
+
+#ifndef SPI1_CS1_PIN
+#define SPI1_CS1_PIN        _BV(PA25_SPI1_NPCS1_B)
+#define SPI1_CS1_PIO_BASE   PIOA_BASE
+#define SPI1_CS1_PSR_OFF    PIO_BSR_OFF
+#endif
+
+#ifndef SPI1_CS2_PIN
+#define SPI1_CS2_PIN        _BV(PA26_SPI1_NPCS2_B)
+#define SPI1_CS2_PIO_BASE   PIOA_BASE
+#define SPI1_CS2_PSR_OFF    PIO_BSR_OFF
+#endif
+
+#ifndef SPI1_CS3_PIN
+#define SPI1_CS3_PIN        _BV(PA29_SPI1_NPCS3_B)
+#define SPI1_CS3_PIO_BASE   PIOA_BASE
+#define SPI1_CS3_PSR_OFF    PIO_BSR_OFF
+#endif
+
+/*@}*/
+
+/*! \name EMAC Interface Peripheral Multiplexing */
+/*@{*/
+#define PB0_ETXCK_EREFCK_A  0
+#define PB1_ETXEN_A         1
+#define PB2_ETX0_A          2
+#define PB3_ETX1_A          3
+#define PB4_ECRS_A          4
+#define PB5_ERX0_A          5
+#define PB6_ERX1_A          6
+#define PB7_ERXER_A         7
+#define PB8_EMDC_A          8
+#define PB9_EMDIO_A         9
+#define PB10_ETX2_A         10
+#define PB11_ETX3_A         11
+#define PB12_ETXER_A        12
+#define PB13_ERX2_A         13
+#define PB14_ERX3_A         14
+#define PB15_ERXDV_ECRSDV_A 15
+#define PB16_ECOL_A         16
+#define PB17_ERXCK_A        17
+#define PB18_EF100_A        18
+/*@}*/
+
+/*! \name Debug Unit Peripheral Multiplexing */
+/*@{*/
+#define PA27_DRXD_A         27
+#define PA28_DTXD_A         28
+/*@}*/
+
+/*! \name Synchronous Serial Controller Peripheral Multiplexing */
+/*@{*/
+#define PA23_TD_A           23  /*!< \brief Transmit data pin. */
+#define PA24_RD_A           24  /*!< \brief Receive data pin. */
+#define PA22_TK_A           22  /*!< \brief Transmit clock pin. */
+#define PA25_RK_A           25  /*!< \brief Receive clock pin. */
+#define PA21_TF_A           21  /*!< \brief Transmit frame sync. pin. */
+#define PA26_RF_A           26  /*!< \brief Receive frame sync. pin. */
+/*@}*/
+
+/*! \name Two Wire Interface Peripheral Multiplexing */
+/*@{*/
+#define PA10_TWD_A          10  /*!< \brief Two wire serial data pin. */
+#define PA11_TWCK_A         11  /*!< \brief Two wire serial clock pin. */
+/*@}*/
+
+/*! \name Timer/Counter Peripheral Multiplexing */
+/*@{*/
+#define PB23_TIOA0_A        23
+#define PB24_TIOB0_A        24
+#define PB12_TCLK0_B        12
+
+#define PB25_TIOA1_A        25
+#define PB26_TIOB1_A        26
+#define PB19_TCLK1_B        19
+
+#define PB27_TIOA2_A        27
+#define PB28_TIOB2_A        28
+#define PA15_TCLK2_B        15
+/*@}*/
+
+/*! \name Clocks, Oscillators and PLLs Peripheral Multiplexing */
+/*@{*/
+#define PB0_PCK0_B          0
+#define PB20_PCK0_B         20
+#define PA13_PCK1_B         13
+#define PB29_PCK1_A         29
+#define PB21_PCK1_B         21
+#define PA30_PCK2_B         30
+#define PB30_PCK2_A         30
+#define PB22_PCK2_B         22
+#define PA27_PCK3_B         27
+/*@}*/
+
+/*! \name Advanced Interrupt Controller Peripheral Multiplexing */
+/*@{*/
+#define PA29_FIQ_A          29
+#define PA30_IRQ0_A         30
+#define PA14_IRQ1_B         14
+/*@}*/
+
+/*! \name ADC Interface Peripheral Multiplexing */
+/*@{*/
+#define PB18_ADTRG_B        18  /*!< \brief ADC trigger pin. */
+/*@}*/
+
+/*! \name CAN Interface Peripheral Multiplexing */
+/*@{*/
+#define PA19_CANRX_A        19
+#define PA20_CANTX_A        20
+/*@}*/
+
+/*! \name PWM Peripheral Multiplexing */
+/*@{*/
+#define PB19_PWM0_A         19
+#define PB27_PWM0_B         27
+#define PB20_PWM1_A         20
+#define PB28_PWM1_B         28
+#define PB21_PWM2_A         21
+#define PB29_PWM2_B         29
+#define PB22_PWM3_A         22
+#define PB30_PWM3_B         30
+/*@}*/
+
+/*@} xgNutArchArmAt91 */
+
+#endif                          /* _ARCH_ARM_AT91SAM7X_H_ */

include/arch/arm/at91sam9260.h

@@ -0,0 +1,430 @@
+#ifndef _ARCH_ARM_SAM9260_H_
+#define _ARCH_ARM_SAM9260_H_
+/*
+ * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91sam9260.h
+ * \brief AT91SAM9260 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91sam9260.h,v $
+ * Revision 1.4  2007/02/15 16:28:07  haraldkipp
+ * Support for system controller interrupts added.
+ *
+ * Revision 1.3  2006/09/29 12:45:08  haraldkipp
+ * Added PIO features and SPI peripheral selections.
+ *
+ * Revision 1.2  2006/09/05 12:32:56  haraldkipp
+ * MIC base address corrected.
+ *
+ * Revision 1.1  2006/08/31 19:04:08  haraldkipp
+ * Added support for the AT91SAM9260 and Atmel's AT91SAM9260 Evaluation Kit.
+ *
+ *
+ * \endverbatim
+ */
+
+#define FLASH_BASE      0x100000UL
+#define RAM_BASE        0x200000UL
+
+#define TC_BASE         0xFFFA0000      /*!< \brief Timer/counter base address. */
+#define UDP_BASE        0xFFFA4000      /*!< \brief USB device port base address. */
+#define MCI_BASE        0xFFFA8000      /*!< \brief MMC/SDCard interface base address. */
+#define TWI_BASE        0xFFFAC000      /*!< \brief Two-wire interface base address. */
+#define USART0_BASE     0xFFFB0000      /*!< \brief USART 0 base address. */
+#define USART1_BASE     0xFFFB4000      /*!< \brief USART 1 base address. */
+#define USART2_BASE     0xFFFB8000      /*!< \brief USART 2 base address. */
+#define SSC_BASE        0xFFFBC000      /*!< \brief Serial synchronous controller base address. */
+#define ISI_BASE        0xFFFC0000      /*!< \brief Image sensor interface base address. */
+#define EMAC_BASE       0xFFFC4000      /*!< \brief EMAC base address. */
+#define SPI0_BASE       0xFFFC8000      /*!< \brief SPI0 0 base address. */
+#define SPI1_BASE       0xFFFCC000      /*!< \brief SPI0 1 base address. */
+#define USART3_BASE     0xFFFD0000      /*!< \brief USART 3 base address. */
+#define USART4_BASE     0xFFFD4000      /*!< \brief USART 4 base address. */
+#define USART5_BASE     0xFFFD8000      /*!< \brief USART 5 base address. */
+#define TC345_BASE      0xFFFDC000      /*!< \brief Timer/counter 3, 4 and 5 base address. */
+#define ADC_BASE        0xFFFE0000      /*!< \brief ADC base address. */
+#define ECC_BASE        0xFFFFE800      /*!< \brief ECC base address. */
+#define SDRAMC_BASE     0xFFFFEA00      /*!< \brief SDRAMC base address. */
+#define SMC_BASE        0xFFFFEC00      /*!< \brief SMC base address. */
+#define MATRIX_BASE     0xFFFFEE00      /*!< \brief MATRIX base address. */
+#define CCFG_BASE       0xFFFFEF10      /*!< \brief CCFG base address. */
+#define AIC_BASE        0xFFFFF000      /*!< \brief AIC base address. */
+#define DBGU_BASE       0xFFFFF200      /*!< \brief DBGU base address. */
+#define PIOA_BASE       0xFFFFF400      /*!< \brief PIO A base address. */
+#define PIOB_BASE       0xFFFFF600      /*!< \brief PIO B base address. */
+#define PIOC_BASE       0xFFFFF800      /*!< \brief PIO C base address. */
+#define PMC_BASE        0xFFFFFC00      /*!< \brief PMC base address. */
+#define RSTC_BASE       0xFFFFFD00      /*!< \brief Resect controller register base address. */
+#define RTT_BASE        0xFFFFFD20      /*!< \brief Realtime timer base address. */
+#define PIT_BASE        0xFFFFFD30      /*!< \brief Periodic interval timer base address. */
+#define WDT_BASE        0xFFFFFD40      /*!< \brief Watch Dog register base address. */
+
+#define PERIPH_RPR_OFF  0x00000100      /*!< \brief Receive pointer register offset. */
+#define PERIPH_RCR_OFF  0x00000104      /*!< \brief Receive counter register offset. */
+#define PERIPH_TPR_OFF  0x00000108      /*!< \brief Transmit pointer register offset. */
+#define PERIPH_TCR_OFF  0x0000010C      /*!< \brief Transmit counter register offset. */
+#define PERIPH_RNPR_OFF 0x00000110      /*!< \brief Receive next pointer register offset. */
+#define PERIPH_RNCR_OFF 0x00000114      /*!< \brief Receive next counter register offset. */
+#define PERIPH_TNPR_OFF 0x00000118      /*!< \brief Transmit next pointer register offset. */
+#define PERIPH_TNCR_OFF 0x0000011C      /*!< \brief Transmit next counter register offset. */
+#define PERIPH_PTCR_OFF 0x00000120      /*!< \brief PDC transfer control register offset. */
+#define PERIPH_PTSR_OFF 0x00000124      /*!< \brief PDC transfer status register offset. */
+
+#define PDC_RXTEN       0x00000001      /*!< \brief Receiver transfer enable. */
+#define PDC_RXTDIS      0x00000002      /*!< \brief Receiver transfer disable. */
+#define PDC_TXTEN       0x00000100      /*!< \brief Transmitter transfer enable. */
+#define PDC_TXTDIS      0x00000200      /*!< \brief Transmitter transfer disable. */
+
+#define DBGU_HAS_PDC
+#define SPI_HAS_PDC
+#define SSC_HAS_PDC
+#define USART_HAS_PDC
+#define MCI_HAS_PDC
+
+#define PIO_HAS_MULTIDRIVER
+#define PIO_HAS_PULLUP
+#define PIO_HAS_PERIPHERALSELECT
+#define PIO_HAS_OUTPUTWRITEENABLE
+
+#include <arch/arm/at91_tc.h>
+#include <arch/arm/at91_us.h>
+#include <arch/arm/at91_dbgu.h>
+#include <arch/arm/at91_emac.h>
+#include <arch/arm/at91_spi.h>
+#include <arch/arm/at91_aic.h>
+#include <arch/arm/at91_pio.h>
+#include <arch/arm/at91_pmc.h>
+#include <arch/arm/at91_rstc.h>
+#include <arch/arm/at91_wdt.h>
+#include <arch/arm/at91_ssc.h>
+#include <arch/arm/at91_twi.h>
+#include <arch/arm/at91_smc.h>
+#include <arch/arm/at91_mci.h>
+#include <arch/arm/at91_matrix.h>
+#include <arch/arm/at91_ccfg.h>
+#include <arch/arm/at91_sdramc.h>
+
+/*! \addtogroup xgNutArchArmAt91Sam9260 */
+/*@{*/
+
+/*! \name Peripheral Identifiers and Interrupts */
+/*@{*/
+#define FIQ_ID      0           /*!< \brief Fast interrupt. */
+#define PIOA_ID     2           /*!< \brief Parallel I/O controller A. */
+#define PIOB_ID     3           /*!< \brief Parallel I/O controller B. */
+#define PIOC_ID     4           /*!< \brief Parallel I/O controller C. */
+#define ADC_ID      5           /*!< \brief Analog to digital converter. */
+#define US0_ID      6           /*!< \brief USART 0. */
+#define US1_ID      7           /*!< \brief USART 1. */
+#define US2_ID      8           /*!< \brief USART 2. */
+#define MCI_ID      9           /*!< \brief MMC interface. */
+#define UDP_ID      10          /*!< \brief USB device port. */
+#define TWI_ID      11          /*!< \brief Two wire interface. */
+#define SPI0_ID     12          /*!< \brief Serial peripheral 0. */
+#define SPI1_ID     13          /*!< \brief Serial peripheral 1. */
+#define SSC_ID      14          /*!< \brief Serial peripheral interface. */
+#define TC0_ID      17          /*!< \brief Timer/counter 0. */
+#define TC1_ID      18          /*!< \brief Timer/counter 1. */
+#define TC2_ID      19          /*!< \brief Timer/counter 2. */
+#define UHP_ID      20          /*!< \brief USB host port. */
+#define EMAC_ID     21          /*!< \brief Ethernet MAC. */
+#define ISI_ID      22          /*!< \brief Image sensor interface. */
+#define US3_ID      23          /*!< \brief USART 3. */
+#define US4_ID      24          /*!< \brief USART 4. */
+#define US5_ID      25          /*!< \brief USART 5. */
+#define TC3_ID      26          /*!< \brief Timer/counter 3. */
+#define TC4_ID      27          /*!< \brief Timer/counter 4. */
+#define TC5_ID      28          /*!< \brief Timer/counter 5. */
+#define IRQ0_ID     29          /*!< \brief External interrupt 0. */
+#define IRQ1_ID     30          /*!< \brief External interrupt 1. */
+#define IRQ2_ID     31          /*!< \brief External interrupt 2. */
+
+/*@}*/
+
+/*! \name USART Peripheral Multiplexing */
+/*@{*/
+#define PA31_SCK0_A         31  /*!< \brief Channel 0 serial clock pin. */
+#define PB4_TXD0_A          4   /*!< \brief Channel 0 transmit data pin. */
+#define PB5_RXD0_A          5   /*!< \brief Channel 0 receive data pin. */
+#define PB27_CTS0_A         27  /*!< \brief Channel 0 clear to send pin. */
+#define PB26_RTS0_A         26  /*!< \brief Channel 0 request to send pin. */
+#define PB25_RI0_A          25  /*!< \brief Channel 0 ring indicator pin. */
+#define PB22_DSR0_A         22  /*!< \brief Channel 0 data set ready pin. */
+#define PB23_DCD0_A         23  /*!< \brief Channel 0 data carrier detect pin. */
+#define PB24_DTR0_A         24  /*!< \brief Channel 0 data terminal ready pin. */
+
+#define PA29_SCK1_A         29  /*!< \brief Channel 1 serial clock pin. */
+#define PB6_TXD1_A          6   /*!< \brief Channel 1 transmit data pin. */
+#define PB7_RXD1_A          7   /*!< \brief Channel 1 receive data pin. */
+#define PB29_CTS1_A         29  /*!< \brief Channel 1 clear to send pin. */
+#define PB28_RTS1_A         28  /*!< \brief Channel 1 request to send pin. */
+
+#define PA30_SCK2_A         30  /*!< \brief Channel 2 serial clock pin. */
+#define PB8_TXD2_A          8   /*!< \brief Channel 2 transmit data pin. */
+#define PB9_RXD2_A          9   /*!< \brief Channel 2 receive data pin. */
+#define PA5_CTS2_A          5   /*!< \brief Channel 2 clear to send pin. */
+#define PA4_RTS2_A          4   /*!< \brief Channel 2 request to send pin. */
+
+#define PC0_SCK3_B          0   /*!< \brief Channel 3 serial clock pin. */
+#define PB10_TXD3_A         10  /*!< \brief Channel 3 transmit data pin. */
+#define PB11_RXD3_A         11  /*!< \brief Channel 3 receive data pin. */
+#define PC10_CTS3_B         10  /*!< \brief Channel 3 clear to send pin. */
+#define PC8_RTS3_B          8   /*!< \brief Channel 3 request to send pin. */
+
+#define PA31_TXD4_B         31  /*!< \brief Channel 4 transmit data pin. */
+#define PA30_RXD4_B         30  /*!< \brief Channel 4 receive data pin. */
+
+#define PB12_TXD5_A         12  /*!< \brief Channel 5 transmit data pin. */
+#define PB13_RXD5_A         13  /*!< \brief Channel 5 receive data pin. */
+/*@}*/
+
+/*! \name SPI Peripheral Multiplexing */
+/*@{*/
+#define PA0_SPI0_MISO_A     0   /*!< \brief Channel 0 master input slave output pin. */
+#define PA1_SPI0_MOSI_A     1   /*!< \brief Channel 0 master output slave input pin. */
+#define PA2_SPI0_SPCK_A     2   /*!< \brief Channel 0 serial clock pin. */
+#define PA3_SPI0_NPCS0_A    3   /*!< \brief Channel 0 chip select 0 pin. */
+#define PC11_SPI0_NPCS1_B   11  /*!< \brief Channel 0 chip select 1 pin. */
+#define PC16_SPI0_NPCS2_B   16  /*!< \brief Channel 0 chip select 2 pin. */
+#define PC17_SPI0_NPCS3_B   17  /*!< \brief Channel 0 chip select 3 pin. */
+
+#define SPI0_PINS           _BV(PA0_SPI0_MISO_A) | _BV(PA1_SPI0_MOSI_A) | _BV(PA2_SPI0_SPCK_A)
+#define SPI0_PIO_BASE       PIOA_BASE
+#define SPI0_PSR_OFF        PIO_ASR_OFF
+
+#define SPI0_CS0_PIN        _BV(PA3_SPI0_NPCS0_A)
+#define SPI0_CS0_PIO_BASE   PIOA_BASE
+#define SPI0_CS0_PSR_OFF    PIO_ASR_OFF
+
+#define SPI0_CS1_PIN        _BV(PC11_SPI0_NPCS1_B)
+#define SPI0_CS1_PIO_BASE   PIOC_BASE
+#define SPI0_CS1_PSR_OFF    PIO_BSR_OFF
+
+#define PB0_SPI1_MISO_A     0   /*!< \brief Channel 1 master input slave output pin. */
+#define PB1_SPI1_MOSI_A     1   /*!< \brief Channel 1 master output slave input pin. */
+#define PB2_SPI1_SPCK_A     2   /*!< \brief Channel 1 serial clock pin. */
+#define PB3_SPI1_NPCS0_A    3   /*!< \brief Channel 1 chip select 0 pin. */
+#define PC5_SPI1_NPCS1_B    5   /*!< \brief Channel 1 chip select 1 pin. */
+#define PC18_SPI1_NPCS1_B   18  /*!< \brief Channel 1 chip select 1 pin. */
+#define PC4_SPI1_NPCS2_B    4   /*!< \brief Channel 1 chip select 2 pin. */
+#define PC19_SPI1_NPCS2_B   19  /*!< \brief Channel 1 chip select 2 pin. */
+#define PC3_SPI1_NPCS3_B    3   /*!< \brief Channel 1 chip select 3 pin. */
+#define PC20_SPI1_NPCS3_B   20  /*!< \brief Channel 1 chip select 3 pin. */
+
+#define SPI1_PINS           _BV(PB0_SPI1_MISO_A) | _BV(PB1_SPI1_MOSI_A) | _BV(PB2_SPI1_SPCK_A)
+#define SPI1_PIO_BASE       PIOB_BASE
+#define SPI1_PSR_OFF        PIO_ASR_OFF
+
+#define SPI1_CS0_PIN        _BV(PB3_SPI1_NPCS0_A)
+#define SPI1_CS0_PIO_BASE   PIOB_BASE
+#define SPI1_CS0_PSR_OFF    PIO_ASR_OFF
+
+#ifndef SPI1_CS3_PIN
+#define SPI1_CS3_PIN        _BV(PC3_SPI1_NPCS3_B)
+#define SPI1_CS3_PIO_BASE   PIOC_BASE
+#define SPI1_CS3_PSR_OFF    PIO_BSR_OFF
+#endif
+
+/*@}*/
+
+/*! \name Image Sensor Interface Peripheral Multiplexing */
+/*@{*/
+#define PB20_ISI_D0_B       20  /*!< \brief Image sensor data bit 0 pin. */
+#define PB21_ISI_D1_B       21  /*!< \brief Image sensor data bit 1 pin. */
+#define PB22_ISI_D2_B       22  /*!< \brief Image sensor data bit 2 pin. */
+#define PB23_ISI_D3_B       23  /*!< \brief Image sensor data bit 3 pin. */
+#define PB24_ISI_D4_B       24  /*!< \brief Image sensor data bit 4 pin. */
+#define PB25_ISI_D5_B       25  /*!< \brief Image sensor data bit 5 pin. */
+#define PB26_ISI_D6_B       26  /*!< \brief Image sensor data bit 6 pin. */
+#define PB27_ISI_D7_B       27  /*!< \brief Image sensor data bit 7 pin. */
+#define PB10_ISI_D8_B       10  /*!< \brief Image sensor data bit 8 pin. */
+#define PB11_ISI_D9_B       11  /*!< \brief Image sensor data bit 9 pin. */
+#define PB12_ISI_D10_B      12  /*!< \brief Image sensor data bit 10 pin. */
+#define PB13_ISI_D11_B      13  /*!< \brief Image sensor data bit 11 pin. */
+#define PB28_ISI_PCK_B      28  /*!< \brief Image sensor data clock pin. */
+#define PB29_ISI_VSYNC_B    29  /*!< \brief Image sensor vertical sync pin. */
+#define PB30_ISI_HSYNC_B    30  /*!< \brief Image sensor horizontal sync pin. */
+#define PB31_ISI_MCK_B      31  /*!< \brief Image sensor reference clock pin. */
+/*@}*/
+
+/*! \name MultiMedia Card and SDCard Interface Peripheral Multiplexing */
+/*@{*/
+#define PA8_MCCK_A          8   /*!< \brief MultiMedia card clock pin. */
+#define PA7_MCCDA_A         7   /*!< \brief MultiMedia card slot A command pin. */
+#define PA6_MCDA0_A         6   /*!< \brief MultiMedia card slot A data bit 0 pin. */
+#define PA9_MCDA1_A         9   /*!< \brief MultiMedia card slot A data bit 1 pin. */
+#define PA10_MCDA2_A        10  /*!< \brief MultiMedia card slot A data bit 2 pin. */
+#define PA11_MCDA3_A        11  /*!< \brief MultiMedia card slot A data bit 3 pin. */
+#define PA1_MCCDB_B         1   /*!< \brief MultiMedia card slot B command pin. */
+#define PA0_MCDB0_B         0   /*!< \brief MultiMedia card slot B data bit 0 pin. */
+#define PA5_MCDB1_B         5   /*!< \brief MultiMedia card slot B data bit 1 pin. */
+#define PA4_MCDB2_B         4   /*!< \brief MultiMedia card slot B data bit 2 pin. */
+#define PA3_MCDB3_B         3   /*!< \brief MultiMedia card slot B data bit 3 pin. */
+/*@}*/
+
+/*! \name EMAC Interface Peripheral Multiplexing */
+/*@{*/
+#define PA10_ETX2_B         10  /*!< \brief Transmit data bit 2 pin. */
+#define PA11_ETX3_B         11  /*!< \brief Transmit data bit 3 pin. */
+#define PA12_ETX0_A         12  /*!< \brief Transmit data bit 0 pin. */
+#define PA13_ETX1_A         13  /*!< \brief Transmit data bit 1 pin. */
+#define PA14_ERX0_A         14  /*!< \brief Receive data bit 0 pin. */
+#define PA15_ERX1_A         15  /*!< \brief Receive data bit 1 pin. */
+#define PA16_ETXEN_A        16  /*!< \brief Transmit enable pin. */
+#define PA17_ERXDV_A        17  /*!< \brief Data valid pin. */
+#define PA18_ERXER_A        18  /*!< \brief Receive error pin. */
+#define PA19_ETXCK_A        19  /*!< \brief Transmit clock pin. */
+#define PA20_EMDC_A         20  /*!< \brief Management data clock pin. */
+#define PA21_EMDIO_A        21  /*!< \brief Management data I/O pin. */
+#define PA22_ETXER_B        22  /*!< \brief Transmit error pin. */
+#define PA23_ETX2_B         23  /*!< \brief Transmit data bit 2 pin. */
+#define PA24_ETX3_B         24  /*!< \brief Transmit data bit 3 pin. */
+#define PA25_ERX2_B         25  /*!< \brief Receive data bit 2 pin. */
+#define PA26_ERX3_B         26  /*!< \brief Receive data bit 3 pin. */
+#define PA27_ERXCK_B        27  /*!< \brief Receive clock pin. */
+#define PA28_ECRS_B         28  /*!< \brief Carrier sense pin. */
+#define PA29_ECOL_B         29  /*!< \brief Collision detect pin. */
+#define PC21_EF100_B        21  /*!< \brief Force 100Mbit pin. */
+/*@}*/
+
+/*! \name ADC Interface Peripheral Multiplexing */
+/*@{*/
+#define PA22_ADTRG_A        22  /*!< \brief ADC trigger pin. */
+/*@}*/
+
+/*! \name Debug Unit Peripheral Multiplexing */
+/*@{*/
+#define PB14_DRXD_A         14  /*!< \brief Debug unit receive data pin. */
+#define PB15_DTXD_A         15  /*!< \brief Debug unit transmit data pin. */
+/*@}*/
+
+/*! \name Synchronous Serial Controller Peripheral Multiplexing */
+/*@{*/
+#define PB18_TD0_A          18  /*!< \brief Transmit data pin. */
+#define PB19_RD0_A          19  /*!< \brief Receive data pin. */
+#define PB16_TK0_A          16  /*!< \brief Transmit clock pin. */
+#define PB20_RK0_A          20  /*!< \brief Receive clock pin. */
+#define PB17_TF0_A          17  /*!< \brief Transmit frame sync. pin. */
+#define PB21_RF0_A          21  /*!< \brief Receive frame sync. pin. */
+/*@}*/
+
+/*! \name Two Wire Interface Peripheral Multiplexing */
+/*@{*/
+#define PA23_TWD_A          23  /*!< \brief Two wire serial data pin. */
+#define PA24_TWCK_A         24  /*!< \brief Two wire serial clock pin. */
+/*@}*/
+
+/*! \name Timer/Counter Peripheral Multiplexing */
+/*@{*/
+#define PA25_TCLK0_A        25  /*!< \brief Timer/counter 0 external clock input. */
+#define PA26_TIOA0_A        26  /*!< \brief Timer/counter 0 I/O line A. */
+#define PC9_TIOB0_B         9   /*!< \brief Timer/counter 0 I/O line B. */
+
+#define PB6_TCLK1_B         6   /*!< \brief Timer/counter 1 external clock input. */
+#define PA27_TIOA1_A        27  /*!< \brief Timer/counter 1 I/O line A. */
+#define PC7_TIOB1_A         7   /*!< \brief Timer/counter 1 I/O line B. */
+
+#define PB7_TCLK2_B         7   /*!< \brief Timer/counter 2 external clock input. */
+#define PA28_TIOA2_A        28  /*!< \brief Timer/counter 2 I/O line A. */
+#define PC6_TIOB2_A         6   /*!< \brief Timer/counter 2 I/O line B. */
+
+#define PB16_TCLK3_B        16  /*!< \brief Timer/counter 3 external clock input. */
+#define PB0_TIOA3_B         0   /*!< \brief Timer/counter 3 I/O line A. */
+#define PB1_TIOB3_B         1   /*!< \brief Timer/counter 3 I/O line B. */
+
+#define PB17_TCLK4_B        17  /*!< \brief Timer/counter 4 external clock input. */
+#define PB2_TIOA4_B         2   /*!< \brief Timer/counter 4 I/O line A. */
+#define PB18_TIOB4_B        18  /*!< \brief Timer/counter 4 I/O line B. */
+
+#define PC22_TCLK5_B        22  /*!< \brief Timer/counter 5 external clock input. */
+#define PB3_TIOA5_B         3   /*!< \brief Timer/counter 5 I/O line A. */
+#define PB19_TIOB5_B        19  /*!< \brief Timer/counter 5 I/O line B. */
+/*@}*/
+
+/*! \name Clocks, Oscillators and PLLs Peripheral Multiplexing */
+/*@{*/
+#define PB30_PCK0_A         30  /*!< \brief Programmable clock 0 output pin. */
+#define PC1_PCK0_B          1   /*!< \brief Programmable clock 0 output pin. */
+#define PB31_PCK1_A         31  /*!< \brief Programmable clock 1 output pin. */
+#define PC2_PCK1_B          2   /*!< \brief Programmable clock 1 output pin. */
+/*@}*/
+
+/*! \name CompactFlash Peripheral Multiplexing */
+/*@{*/
+#define PC10_A25_CFRNW_A    10  /*!< \brief Read not write pin. */
+#define PC8_NCS4_CFCS0_A    8   /*!< \brief Chip select line 0 pin. */
+#define PC9_NCS5_CFCS1_A    9   /*!< \brief Chip select line 1 pin. */
+#define PC6_CFCE1_B         6   /*!< \brief Chip enable line 1 pin. */
+#define PC7_CFCE2_B         7   /*!< \brief Chip enable line 2 pin. */
+/*@}*/
+
+/*! \name External Bus Interface Peripheral Multiplexing */
+/*@{*/
+#define PC16_D16_A          16  /*!< \brief Data bus bit 16 pin. */
+#define PC17_D17_A          17  /*!< \brief Data bus bit 17 pin. */
+#define PC18_D18_A          18  /*!< \brief Data bus bit 18 pin. */
+#define PC19_D19_A          19  /*!< \brief Data bus bit 19 pin. */
+#define PC20_D20_A          20  /*!< \brief Data bus bit 20 pin. */
+#define PC21_D21_A          21  /*!< \brief Data bus bit 21 pin. */
+#define PC22_D22_A          22  /*!< \brief Data bus bit 22 pin. */
+#define PC23_D23_A          23  /*!< \brief Data bus bit 23 pin. */
+#define PC24_D24_A          24  /*!< \brief Data bus bit 24 pin. */
+#define PC25_D25_A          25  /*!< \brief Data bus bit 25 pin. */
+#define PC26_D26_A          26  /*!< \brief Data bus bit 26 pin. */
+#define PC27_D27_A          27  /*!< \brief Data bus bit 27 pin. */
+#define PC28_D28_A          28  /*!< \brief Data bus bit 28 pin. */
+#define PC29_D29_A          29  /*!< \brief Data bus bit 29 pin. */
+#define PC30_D30_A          30  /*!< \brief Data bus bit 30 pin. */
+#define PC31_D31_A          31  /*!< \brief Data bus bit 31 pin. */
+#define PC4_A23_A           4   /*!< \brief Address bus bit 23 pin. */
+#define PC5_A24_A           5   /*!< \brief Address bus bit 24 pin. */
+#define PC11_NCS2_A         11  /*!< \brief Negated chip select 2 pin. */
+#define PC14_NCS3_NANDCS_A  14  /*!< \brief Negated chip select 3 pin. */
+#define PC13_NCS6_B         13  /*!< \brief Negated chip select 6 pin. */
+#define PC12_NCS7_B         12  /*!< \brief Negated chip select 7 pin. */
+#define PC15_NWAIT_A        15  /*!< \brief External wait signal pin. */
+/*@}*/
+
+/*! \name Advanced Interrupt Controller Peripheral Multiplexing */
+/*@{*/
+#define PC13_FIQ_A          13  /*!< \brief Fast interrupt input pin. */
+#define PC12_IRQ0_A         12  /*!< \brief External interrupt 0 input pin. */
+#define PC15_IRQ1_B         15  /*!< \brief External interrupt 1 input pin. */
+#define PC14_IRQ2_B         14  /*!< \brief External interrupt 2 input pin. */
+/*@}*/
+
+/*@} xgNutArchArmAt91Sam9260 */
+
+#endif                          /* _ARCH_ARM_SAM9260_H_ */

include/arch/arm/at91x40.h

@@ -0,0 +1,134 @@
+#ifndef _ARCH_ARM_AT91X40_H_
+#define _ARCH_ARM_AT91X40_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file arch/arm/at91x40.h
+ * \brief AT91 peripherals.
+ *
+ * \verbatim
+ *
+ * $Log: at91x40.h,v $
+ * Revision 1.4  2006/10/08 16:48:09  haraldkipp
+ * Documentation fixed
+ *
+ * Revision 1.3  2006/08/05 11:56:29  haraldkipp
+ * Old SAM7X leftovers finally removed.
+ * PDC register configuration added.
+ *
+ * Revision 1.2  2006/08/01 07:35:59  haraldkipp
+ * Exclude function prototypes when included by assembler.
+ *
+ * Revision 1.1  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * Revision 1.7  2006/06/28 17:22:34  haraldkipp
+ * Make it compile for AT91SAM7X256.
+ *
+ * Revision 1.6  2006/05/25 09:09:57  haraldkipp
+ * API documentation updated and corrected.
+ *
+ * Revision 1.5  2006/04/07 12:57:00  haraldkipp
+ * Fast interrupt doesn't require to store R8-R12.
+ *
+ * Revision 1.4  2006/03/02 20:02:56  haraldkipp
+ * Added ICCARM interrupt entry code. Probably not working, because I
+ * excluded an immediate load.
+ *
+ * Revision 1.3  2006/01/05 16:52:49  haraldkipp
+ * Baudrate calculation is now based on NutGetCpuClock().
+ * The AT91_US_BAUD macro had been marked deprecated.
+ *
+ * Revision 1.2  2005/11/20 14:44:14  haraldkipp
+ * Register offsets added.
+ *
+ * Revision 1.1  2005/10/24 10:31:13  haraldkipp
+ * Moved from parent directory.
+ *
+ *
+ * \endverbatim
+ */
+
+/*! \addtogroup xgNutArchArmAt91x40 */
+/*@{*/
+
+/*! \name Peripheral Identifiers and Interrupts */
+/*@{*/
+#define FIQ_ID      0           /*!< \brief Fast interrupt ID. */
+#define SWIRQ_ID    1           /*!< \brief Software interrupt ID. */
+#define US0_ID      2           /*!< \brief USART 0 ID. */
+#define US1_ID      3           /*!< \brief USART 1 ID. */
+#define TC0_ID      4           /*!< \brief Timer 0 ID. */
+#define TC1_ID      5           /*!< \brief Timer 1 ID. */
+#define TC2_ID      6           /*!< \brief Timer 2 ID. */
+#define WDI_ID      7           /*!< \brief Watchdog interrupt ID. */
+#define PIO_ID      8           /*!< \brief Parallel I/O controller ID. */
+#define IRQ0_ID     16          /*!< \brief External interrupt 0 ID. */
+#define IRQ1_ID     17          /*!< \brief External interrupt 1 ID. */
+#define IRQ2_ID     18          /*!< \brief External interrupt 2 ID. */
+/*@}*/
+
+#define EBI_BASE        0xFFE00000      /*!< \brief EBI base address. */
+#define SF_BASE         0xFFF00000      /*!< \brief Special function register base address. */
+#define USART1_BASE     0xFFFCC000      /*!< \brief USART 1 base address. */
+#define USART0_BASE     0xFFFD0000      /*!< \brief USART 0 base address. */
+#define TC_BASE         0xFFFE0000      /*!< \brief TC base address. */
+#define PIO_BASE        0xFFFF0000      /*!< \brief PIO base address. */
+#define PS_BASE         0xFFFF4000      /*!< \brief PS base address. */
+#define WD_BASE         0xFFFF8000      /*!< \brief Watch Dog register base address. */
+#define AIC_BASE        0xFFFFF000      /*!< AIC base address. */
+
+#define PERIPH_RPR_OFF  0x00000030      /*!< \brief Receive pointer register offset. */
+#define PERIPH_RCR_OFF  0x00000034      /*!< \brief Receive counter register offset. */
+#define PERIPH_TPR_OFF  0x00000038      /*!< \brief Transmit pointer register offset. */
+#define PERIPH_TCR_OFF  0x0000003C      /*!< \brief Transmit counter register offset. */
+
+#define USART_HAS_PDC
+
+#include <arch/arm/at91_ebi.h>
+#include <arch/arm/at91_sf.h>
+#include <arch/arm/at91_us.h>
+#include <arch/arm/at91_tc.h>
+#include <arch/arm/at91_pio.h>
+#include <arch/arm/at91_ps.h>
+#include <arch/arm/at91_wd.h>
+#include <arch/arm/at91_aic.h>
+
+/*@} xgNutArchArmAt91 */
+
+#ifndef __ASSEMBLER__
+extern void McuInit(void);
+#endif
+
+#endif                          /* _ARCH_ARM_AT91X40_H_ */

include/arch/arm/atom.h

@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: atom.h,v $
+ * Revision 1.3  2006/03/02 20:03:39  haraldkipp
+ * Added ICCARM inline assembly for NutEnter/ExitCritical(). Also fixed
+ * SF 1440949 (FIQ never enabled).
+ *
+ * Revision 1.2  2005/07/26 15:47:06  haraldkipp
+ * AtomicInc() and AtomicDec() are no longer required by Nut/Net.
+ * Removed to simplify the porting job. Broken applications should
+ * implement their own version.
+ *
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.1  2005/05/27 17:41:52  drsung
+ * Moved the file.
+ *
+ * Revision 1.1  2005/05/26 10:08:42  drsung
+ * Moved the platform dependend code from include/sys/atom.h to this file.
+ *
+ *
+ */
+
+#ifndef _SYS_ATOM_H_
+#error "Do not include this file directly. Use sys/atom.h instead!"
+#endif
+
+#ifdef __GNUC__
+
+#define NutEnterCritical() \
+        asm volatile (             \
+                "@ NutEnterCritical"      "\n\t"      \
+                "mrs r0, cpsr"      "\n\t"      \
+                "orr r0, r0, #0xC0" "\n\t"  \
+                "msr cpsr, r0"      "\n\t"  \
+                ::: "r0" )
+
+#define NutExitCritical() \
+        asm volatile (             \
+                "@ NutExitCritical"      "\n\t"      \
+                "mrs r0, cpsr"      "\n\t"      \
+                "bic r0, r0, #0xC0" "\n\t"  \
+                "msr cpsr, r0"      "\n\t"  \
+                ::: "r0" )
+
+#define NutJumpOutCritical()    NutExitCritical()
+
+#else /* __IMAGECRAFT__ */
+
+#define NutEnterCritical() \
+        asm("; NutEnterCritical\n" \
+            "mrs r12, cpsr\n" \
+            "orr r12, r12, #0xC0\n" \
+            "msr cpsr_c, r12")
+
+#define NutExitCritical() \
+        asm("; NutExitCritical\n" \
+            "mrs r12, cpsr\n" \
+            "bic r12, r12, #0xC0\n" \
+            "msr cpsr_c, r12")
+
+#endif

include/arch/arm/gba.h

@@ -0,0 +1,241 @@
+#ifndef _ARCH_GBA_H_
+#define _ARCH_GBA_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: gba.h,v $
+ * Revision 1.1  2005/10/24 10:31:13  haraldkipp
+ * Moved from parent directory.
+ *
+ * Revision 1.2  2005/04/05 17:50:47  haraldkipp
+ * Use register names in gba.h.
+ *
+ * Revision 1.1  2004/11/24 15:26:34  haraldkipp
+ * Will fill this later
+ *
+ */
+
+
+/*!
+ * \brief Internal work RAM
+ */
+#define WRAM_START      0x03000000      /* Start of internal work RAM */
+#define WRAM_END        (WRAM_START + 0x8000)   /* End of internal work RAM */
+#define INT_VECTOR      (WRAM_END - 4)  /* Interrupt vector address. */
+
+/*!
+ * \brief Display control
+ */
+#define REG_DISPCNT     0x04000000      /* Display control */
+#define REG_STAT        0x04000004      /* Display status */
+#define REG_VCOUNT      0x04000006      /* Vertical counter */
+#define REG_BG0CNT      0x04000008      /* BG 0 control */
+#define REG_BG1CNT      0x0400000a      /* BG 1 control */
+#define REG_BG2CNT      0x0400000c      /* BG 2 control */
+#define REG_BG3CNT      0x0400000e      /* BG 3 control */
+#define REG_BG0HOFS     0x04000010      /* BG 0 horizontal offset */
+#define REG_BG0VOFS     0x04000012      /* BG 0 vertical offset */
+#define REG_BG1HOFS     0x04000014      /* BG 1 horizontal offset */
+#define REG_BG1VOFS     0x04000016      /* BG 1 vertical offset */
+#define REG_BG2HOFS     0x04000018      /* BG 2 horizontal offset */
+#define REG_BG2VOFS     0x0400001a      /* BG 2 vertical offset */
+#define REG_BG3HOFS     0x0400001c      /* BG 3 horizontal offset */
+#define REG_BG3VOFS     0x0400001e      /* BG 3 vertical offset */
+#define REG_BG2PA       0x04000020      /* BG 2 Rotation/scaling parameter A */
+#define REG_BG2PB       0x04000022      /* BG 2 Rotation/scaling parameter B */
+#define REG_BG2PC       0x04000024      /* BG 2 Rotation/scaling parameter C */
+#define REG_BG2PD       0x04000026      /* BG 2 Rotation/scaling parameter D */
+#define REG_BG2X        0x04000028      /* BG 2 Reference point X coordinate */
+#define REG_BG2Y        0x0400002c      /* BG 2 Reference point Y coordinate */
+#define REG_BG3PA       0x04000030      /* BG 3 Rotation/scaling parameter A */
+#define REG_BG3PB       0x04000032      /* BG 3 Rotation/scaling parameter B */
+#define REG_BG3PC       0x04000034      /* BG 3 Rotation/scaling parameter C */
+#define REG_BG3PD       0x04000036      /* BG 3 Rotation/scaling parameter D */
+#define REG_BG3X        0x04000038      /* BG 3 Reference point X coordinate */
+#define REG_BG3Y        0x0400003c      /* BG 3 Reference point Y coordinate */
+#define REG_WINCNT      0x04000040      /* Window control */
+#define REG_WININ       0x04000048      /* Inside window control */
+#define REG_WINOUT      0x0400004a      /* Outside window control */
+#define REG_MOSAIC      0x0400004c      /* Mosaic size */
+#define REG_BLDCNT      0x04000050      /* Blending control */
+#define REG_BLDALPHA    0x04000052      /* Alpha blending */
+#define REG_BLDY        0x04000054      /* Brightness fading */
+
+/*!
+ * \brief Sound control
+ */
+#define REG_SOUND1CNT   0x04000060      /* Channel 1 control */
+#define REG_SOUND2CNT   0x04000068      /* Channel 2 control */
+#define REG_SOUND3CNT   0x04000070      /* Channel 3 control */
+#define REG_SOUND4CNT   0x04000078      /* Channel 4 control */
+#define REG_SOUNDCNT    0x04000080      /* Sound control */
+#define REG_SOUNDBIAS   0x04000088      /* Sound PWM control */
+#define REG_WAVE_RAM0   0x04000090      /* Channel 3 wave pattern RAM bank 0 */
+#define REG_WAVE_RAM1   0x04000094      /* Channel 3 wave pattern RAM bank 1 */
+#define REG_WAVE_RAM2   0x04000098      /* Channel 3 wave pattern RAM bank 2 */
+#define REG_WAVE_RAM3   0x0400009c      /* Channel 3 wave pattern RAM bank 3 */
+#define REG_FIFO_A      0x040000a0      /* Channel A FIFO */
+#define REG_FIFO_B      0x040000a4      /* Channel B FIFO */
+
+/*!
+ * \brief DMA control
+ */
+#define REG_DMA0SAD     0x040000b0      /* DMA 0 source address */
+#define REG_DMA0DAD     0x040000b4      /* DMA 0 destination address */
+#define REG_DMA0CNT     0x040000b8      /* DMA 0 word count */
+#define REG_DMA1SAD     0x040000bc      /* DMA 1 source address */
+#define REG_DMA1DAD     0x040000c0      /* DMA 1 destination address */
+#define REG_DMA1CNT     0x040000c4      /* DMA 1 word count */
+#define REG_DMA2SAD     0x040000c8      /* DMA 2 source address */
+#define REG_DMA2DAD     0x040000cc      /* DMA 2 destination address */
+#define REG_DMA2CNT     0x040000d0      /* DMA 2 word count */
+#define REG_DMA3SAD     0x040000d4      /* DMA 3 source address */
+#define REG_DMA3DAD     0x040000d8      /* DMA 3 destination address */
+#define REG_DMA3CNT     0x040000dc      /* DMA 3 word count */
+
+/*!
+ * \brief Timer control
+ */
+#define REG_TMR0CNT     0x04000100      /* Timer 0 control */
+#define REG_TMR1CNT     0x04000104      /* Timer 1 control */
+#define REG_TMR2CNT     0x04000108      /* Timer 2 control */
+#define REG_TMR3CNT     0x0400010c      /* Timer 3 control */
+
+/*!
+ * \brief Serial communication control
+ */
+#define REG_SIODATA32   0x04000120      /* 32-bit serial data */
+#define REG_SIOCNT      0x04000128      /* Serial communication control */
+#define REG_SIODATA8    0x0400012a      /* 8-bit serial data */
+
+/*!
+ * \brief Keyboard control
+ */
+#define REG_KEYINPUT    0x04000130      /* Key status */
+#define REG_KEYCNT      0x04000132      /* Key control */
+
+/*!
+ * \brief General I/O control
+ */
+#define REG_RCNT        0x04000134      /* General I/O control */
+
+/*!
+ * \brief JOY Bus control
+ */
+#define REG_JOYCNT      0x04000140      /* JOY Bus control */
+#define REG_JOYSTAT     0x04000158      /* JOY Bus status */
+#define REG_JOY_RECV    0x04000150      /* JOY Bus receive data */
+#define REG_JOY_TRANS   0x04000154      /* JOY Bus transmit data */
+
+/*!
+ * \brief Interrupt control
+ */
+#define REG_IE          0x04000200      /* Interrupt enable */
+#define REG_IF          0x04000202      /* Interrupt flags */
+#define REG_WAITCNT     0x04000204      /* Game Pak wait state control */
+#define REG_IME         0x04000208      /* Interrupt master enable */
+
+/*!
+ * \brief Interrupt flags.
+ */
+#define INT_VBLANK      0x0001      /* V blank interrupt flag. */
+#define INT_HBLANK      0x0002      /* H blank interrupt flag. */
+#define INT_VCOUNT      0x0004      /* V counter interrupt flag. */
+#define INT_TMR0        0x0008      /* Timer 0 interrupt flag. */
+#define INT_TMR1        0x0010      /* Timer 1 interrupt flag. */
+#define INT_TMR2        0x0020      /* Timer 2 interrupt flag. */
+#define INT_TMR3        0x0040      /* Timer 3 interrupt flag. */
+#define INT_SIO         0x0080      /* Serial communication interrupt flag. */
+#define INT_DMA0        0x0100      /* DMA 0 interrupt flag. */
+#define INT_DMA1        0x0200      /* DMA 1 interrupt flag. */
+#define INT_DMA2        0x0400      /* DMA 2 interrupt flag. */
+#define INT_DMA3        0x0800      /* DMA 3 interrupt flag. */
+#define INT_KEYPAD      0x1000      /* Key Pad interrupt flag. */
+#define INT_GAMEPAK     0x2000      /* Game Pak interrupt flag. */
+
+/*!
+ * \brief Power management control
+ */
+#define REG_HALTCNT     0x04000300      /* Power down control */
+
+
+#define outw(_reg, _val)    (*((volatile unsigned short *)(_reg)) = (_val))
+#define outdw(_reg, _val)   (*((volatile unsigned long *)(_reg)) = (_val))
+#define inw(_reg)           (*((volatile unsigned short *)(_reg)))
+#define indw(_reg)          (*((volatile unsigned long *)(_reg)))
+
+
+#define GBAKEY_A        0x0001
+#define GBAKEY_B        0x0002
+#define GBAKEY_SELECT   0x0003
+#define GBAKEY_START    0x0008
+#define GBAKEY_RIGHT    0x0010
+#define GBAKEY_LEFT     0x0020
+#define GBAKEY_UP       0x0040
+#define GBAKEY_DOWN     0x0080
+#define GBAKEY_R        0x0100
+#define GBAKEY_L        0x0200
+
+/*!
+ * \brief Timer control.
+ */
+#define TMR_PRE_64      0x00010000  /* Prescaler 64 */
+#define TMR_PRE_256     0x00020000  /* Prescaler 256 */
+#define TMR_PRE_1024    0x00030000  /* Prescaler 1024 */
+#define TMR_IRQ_ENA     0x00400000  /* Interrupt request enable */
+#define TMR_ENA         0x00800000  /* Timer enable. */
+
+/*!
+ * \brief SIO control.
+ */
+#define SIO_BAUD_9600     0x0000
+#define SIO_BAUD_38400    0x0001
+#define SIO_BAUD_57600    0x0002
+#define SIO_BAUD_115200   0x0003
+#define SIO_CTS_ENA       0x0004
+#define SIO_PARITY_ODD    0x0008
+#define SIO_TX_FULL       0x0010
+#define SIO_RX_EMPTY      0x0020
+#define SIO_ERROR         0x0040
+#define SIO_DATA_8BIT     0x0080
+#define SIO_FIFO_ENA      0x0100
+#define SIO_PARITY_ENA    0x0200
+#define SIO_SEND_ENA      0x0400
+#define SIO_RECV_ENA      0x0800
+#define SIO_MODE_32BIT    0x1000
+#define SIO_MODE_MULTI    0x2000
+#define SIO_MODE_UART     0x3000
+#define SIO_IRQ_ENA       0x4000
+
+#endif

include/arch/arm/irqreg.h

@@ -0,0 +1,188 @@
+#ifndef _DEV_IRQREG_ARM_H_
+#define _DEV_IRQREG_ARM_H_
+
+/*
+ * Copyright (C) 2001-2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: irqreg.h,v $
+ * Revision 1.10  2007/02/15 16:29:23  haraldkipp
+ * Support for system controller interrupts added.
+ *
+ * Revision 1.9  2006/09/29 12:34:59  haraldkipp
+ * Basic AT91 SPI support added.
+ *
+ * Revision 1.8  2006/09/08 16:47:49  haraldkipp
+ * For some reason the SSC driver for SAM7X had not been included.
+ *
+ * Revision 1.7  2006/09/05 12:33:45  haraldkipp
+ * SSC interrupt handler added.
+ *
+ * Revision 1.6  2006/08/31 19:04:08  haraldkipp
+ * Added support for the AT91SAM9260 and Atmel's AT91SAM9260 Evaluation Kit.
+ *
+ * Revision 1.5  2006/07/05 07:45:28  haraldkipp
+ * Split on-chip interface definitions.
+ *
+ * Revision 1.4  2006/06/28 17:22:34  haraldkipp
+ * Make it compile for AT91SAM7X256.
+ *
+ * Revision 1.3  2006/02/23 15:33:59  haraldkipp
+ * Support for Philips LPC2xxx Family and LPC-E2294 Board from Olimex added.
+ * Many thanks to Michael Fischer for this port.
+ *
+ * Revision 1.2  2005/10/24 10:26:21  haraldkipp
+ * AT91 handlers added.
+ *
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ * Revision 1.3  2005/04/05 17:52:40  haraldkipp
+ * Much better implementation of GBA interrupt registration.
+ *
+ * Revision 1.2  2004/09/08 10:52:31  haraldkipp
+ * Tyou's support for the SAMSUNG S3C45
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ *
+ */
+
+#ifdef S3C4510B
+#include "s3c4510b_irqreg.h"
+
+#elif defined(MCU_GBA)
+
+extern IRQ_HANDLER sig_VBLANK;
+extern IRQ_HANDLER sig_HBLANK;
+extern IRQ_HANDLER sig_VCOUNT;
+extern IRQ_HANDLER sig_TMR0;
+extern IRQ_HANDLER sig_TMR1;
+extern IRQ_HANDLER sig_TMR2;
+extern IRQ_HANDLER sig_TMR3;
+extern IRQ_HANDLER sig_SIO;
+extern IRQ_HANDLER sig_DMA0;
+extern IRQ_HANDLER sig_DMA1;
+extern IRQ_HANDLER sig_DMA2;
+extern IRQ_HANDLER sig_DMA3;
+extern IRQ_HANDLER sig_KEYPAD;
+extern IRQ_HANDLER sig_GAMEPAK;
+
+extern void InitIrqHandler(void);
+
+#elif defined(MCU_AT91R40008)
+
+extern IRQ_HANDLER sig_FIQ;
+extern IRQ_HANDLER sig_SWIRQ;
+extern IRQ_HANDLER sig_UART0;
+extern IRQ_HANDLER sig_UART1;
+extern IRQ_HANDLER sig_TC0;
+extern IRQ_HANDLER sig_TC1;
+extern IRQ_HANDLER sig_TC2;
+extern IRQ_HANDLER sig_WDI;
+extern IRQ_HANDLER sig_PIO;
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_INTERRUPT2;
+
+#elif defined(MCU_LPC2XXX)
+
+extern IRQ_HANDLER sig_UART0;
+extern IRQ_HANDLER sig_UART1;
+extern IRQ_HANDLER sig_TC0;
+extern IRQ_HANDLER sig_TC1;
+extern IRQ_HANDLER sig_WDI;
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_INTERRUPT2;
+extern IRQ_HANDLER sig_INTERRUPT2;
+
+#elif defined(MCU_AT91SAM7X256)
+
+extern IRQ_HANDLER sig_FIQ;
+extern IRQ_HANDLER sig_SYS;
+extern IRQ_HANDLER sig_UART0;
+extern IRQ_HANDLER sig_UART1;
+extern IRQ_HANDLER sig_TC0;
+extern IRQ_HANDLER sig_TC1;
+extern IRQ_HANDLER sig_TC2;
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_EMAC;
+extern IRQ_HANDLER sig_PIO;
+extern IRQ_HANDLER sig_SWIRQ;
+extern IRQ_HANDLER sig_SSC;
+
+/*
+ * Registered system interrupt handler information structure.
+ */
+typedef struct {
+    void *sir_arg;
+    void (*sir_handler) (void *);
+    int sir_enabled;
+} SYSIRQ_HANDLER;
+
+extern SYSIRQ_HANDLER syssig_DBGU;
+extern SYSIRQ_HANDLER syssig_MC;
+extern SYSIRQ_HANDLER syssig_PIT;
+extern SYSIRQ_HANDLER syssig_PMC;
+extern SYSIRQ_HANDLER syssig_RSTC;
+extern SYSIRQ_HANDLER syssig_RTT;
+extern SYSIRQ_HANDLER syssig_WDT;
+
+extern int NutRegisterSysIrqHandler(SYSIRQ_HANDLER * sysirq, void (*handler) (void *), void *arg);
+extern int NutSysIrqEnable(SYSIRQ_HANDLER * sysirq);
+extern int NutSysIrqDisable(SYSIRQ_HANDLER * sysirq);
+
+#elif defined(MCU_AT91SAM9260)
+
+extern IRQ_HANDLER sig_FIQ;
+extern IRQ_HANDLER sig_UART0;
+extern IRQ_HANDLER sig_UART1;
+extern IRQ_HANDLER sig_TC0;
+extern IRQ_HANDLER sig_TC1;
+extern IRQ_HANDLER sig_TC2;
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_EMAC;
+extern IRQ_HANDLER sig_PIO;
+extern IRQ_HANDLER sig_SWIRQ;
+extern IRQ_HANDLER sig_SSC;
+extern IRQ_HANDLER sig_SPI0;
+extern IRQ_HANDLER sig_SPI1;
+
+#else
+#warning "No MCU defined"
+#endif
+
+#endif

include/arch/arm/lpc2xxx.h

@@ -0,0 +1,83 @@
+/****************************************************************************
+*  This file is part of the Ethernut port for the LPC2XXX
+*
+*  Copyright (c) 2005 by Michael Fischer. All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*  
+*  1. Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*  2. Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the distribution.
+*  3. Neither the name of the author nor the names of its contributors may 
+*     be used to endorse or promote products derived from this software 
+*     without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  SUCH DAMAGE.
+*
+****************************************************************************
+*
+*  History:
+*
+*  24.09.05  mifi   First Version
+*                   The CrossWorks for ARM toolchain will be used.
+****************************************************************************/
+#ifndef __LPC2XXX_H__
+#define __LPC2XXX_H__
+
+/*
+ * Include the header file for the lpc22xx, from CrossWorks
+ */
+#include <targets/lpc22xx.h>
+
+/*
+ * For the Debug macro we must include cross_studio_io.h
+ */
+#define Debug             debug_printf
+
+#define VIC_WDT           0
+#define VIC_TIMER0        4
+#define VIC_TIMER1        5
+#define VIC_UART0         6
+#define VIC_UART1         7
+#define VIC_PWM0          8
+#define VIC_I2C           9
+#define VIC_SPI0          10
+#define VIC_SPI1          11
+#define VIC_PLL           12
+#define VIC_RTC           13
+#define VIC_EINT0         14
+#define VIC_EINT1         15
+#define VIC_EINT2         16
+#define VIC_EINT3         17
+
+#define IRQ_ENTRY()
+#define IRQ_EXIT()
+
+/*!
+ * \brief Case insensitive string comparisions.
+ *
+ * Not supported by CrossWorks and temporarly redirected to
+ * the case sensitive routines.
+ *
+ */
+#define strcasecmp(s1, s2)      strcmp(s1, s2)
+#define strncasecmp(s1, s2, n)  strncmp(s1, s2, n)
+
+#endif /* __LPC2XXX_H__ */
+/*** EOF ***/
+

include/arch/arm/timer.h

@@ -0,0 +1,71 @@
+#ifndef _ARCH_ARM_TIMER_H_
+#define _ARCH_ARM_TIMER_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: timer.h,v $
+ * Revision 1.4  2006/09/29 12:45:35  haraldkipp
+ * Include clock configuration.
+ *
+ * Revision 1.3  2006/08/31 18:59:50  haraldkipp
+ * Added support for the AT91SAM9260. We now determine between processor and
+ * master clock. A new API function At91GetMasterClock() had been added to
+ * query the latter.
+ *
+ * Revision 1.2  2006/02/23 15:33:59  haraldkipp
+ * Support for Philips LPC2xxx Family and LPC-E2294 Board from Olimex added.
+ * Many thanks to Michael Fischer for this port.
+ *
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ */
+
+#include <cfg/clock.h>
+
+#ifdef MCU_LPC2XXX
+void NutEnableTimerIrq (void);
+void NutDisableTimerIrq (void);
+#else
+#define NutEnableTimerIrq()     NutEnterCritical()
+#define NutDisableTimerIrq()    NutExitCritical()
+#endif
+
+#if defined(AT91_PLL_MAINCK)
+extern u_long At91GetMasterClock(void);
+#endif
+
+#endif
+
+

include/arch/avr.h

@@ -0,0 +1,226 @@
+#ifndef _ARCH_AVR_H_
+#define _ARCH_AVR_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: avr.h,v $
+ * Revision 1.14  2006/02/08 15:20:22  haraldkipp
+ * ATmega2561 Support
+ *
+ * Revision 1.13  2005/10/24 10:42:48  haraldkipp
+ * Definitions distributed to avr/icc.h and avr/gcc.h.
+ *
+ * Revision 1.12  2005/10/04 05:21:52  hwmaier
+ * Added TIFR definition for AT09CAN128
+ *
+ * Revision 1.11  2005/08/02 17:46:48  haraldkipp
+ * Major API documentation update.
+ *
+ * Revision 1.10  2005/02/22 17:03:02  freckle
+ * changed avr-libc-1.2 test to use eeprom_rb, as other test was wrong on
+ * 1.0.5
+ *
+ * Revision 1.9  2005/02/22 16:22:21  freckle
+ * Added cpp test to guess avr-libc-version required  to specify twi.h path
+ *
+ * Revision 1.8  2005/02/10 07:06:48  hwmaier
+ * Changes to incorporate support for AT90CAN128 CPU
+ *
+ * Revision 1.7  2005/01/10 12:40:15  olereinhardt
+ * Included check if atof is just defined (needed by new avr-libc versions on debian unstable)
+ *
+ * Revision 1.6  2004/07/09 19:51:34  freckle
+ * Added new function NutThreadSetSleepMode to tell nut/os to set the MCU
+ * into sleep mode when idle (avr-gcc && avr128 only)
+ *
+ * Revision 1.5  2004/05/23 14:30:32  drsung
+ * Added some macros, because they are no longer available since version 1.1.0 of avr-libc.
+ *
+ * Revision 1.4  2004/03/18 15:53:42  haraldkipp
+ * ICCAVR failed to compile
+ *
+ * Revision 1.3  2004/03/18 09:57:01  haraldkipp
+ * Architecture required in UserConf.mk
+ *
+ * Revision 1.2  2004/03/17 14:54:00  haraldkipp
+ * Compiling for AVR works again
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ * Revision 1.1  2004/02/01 18:49:47  haraldkipp
+ * Added CPU family support
+ *
+ */
+
+#if defined(__IMAGECRAFT__)
+#include <arch/avr/icc.h>
+#elif defined(__GNUC__)
+#include <arch/avr/gcc.h>
+#else
+#error "Unable to determine AVR compiler."
+#endif
+
+/*!
+ * \brief Specify AVR target.
+ *
+ * Only GCC provides this as a predefined macro. Nut/OS explicitly
+ * re-defines this, so that it will be available for all compilers.
+ */
+#undef __AVR__
+#define __AVR__
+
+
+/*
+ * Since version 1.1.0 of avr-libc, some former deprecated macros are deleted.
+ * But we need them futher on, so they are defined here.
+ */
+#ifndef cbi
+#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
+#endif
+#ifndef sbi
+#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
+#endif
+#ifndef inb
+#define inb(sfr) _SFR_BYTE(sfr)
+#endif
+#ifndef outb
+#define outb(sfr, val) (_SFR_BYTE(sfr) = (val))
+#endif
+#ifndef outp
+#define outp(val, sfr) outb(sfr, val)
+#endif
+#ifndef inp
+#define inp(sfr) inb(sfr)
+#endif
+#ifndef BV
+#define BV(bit) _BV(bit)
+#endif
+#ifndef inw
+#define inw(sfr) _SFR_WORD(sfr)
+#endif
+#ifndef outw
+#define outw(sfr, val) (_SFR_WORD(sfr) = (val))
+#endif
+#ifndef PRG_RDB
+#define PRG_RDB(addr)       pgm_read_byte(addr)
+#endif
+
+#define __bss_end	__heap_start
+extern void *__heap_start;
+
+#ifdef __AVR_ENHANCED__
+
+/* Nut/OS is still using the original ATmega103 register names for
+   backward compatibility. */
+#ifndef UDR
+#define UDR     UDR0
+#endif
+#ifndef UBRR
+#define UBRR    UBRR0L
+#endif
+#ifndef USR
+#define USR     UCSR0A
+#endif
+#ifndef UCR
+#define UCR     UCSR0B
+#endif
+#ifndef EICR
+#define EICR    EICRB
+#endif
+#ifndef RXC
+#define RXC     RXC0
+#endif
+#ifndef UDRE
+#define UDRE    UDRE0
+#endif
+#ifndef FE
+#define FE      FE0
+#endif
+#ifndef DOR
+#define DOR     DOR0
+#endif
+#ifndef RXCIE
+#define RXCIE   RXCIE0
+#endif
+#ifndef TXCIE
+#define TXCIE   TXCIE0
+#endif
+#ifndef UDRIE
+#define UDRIE   UDRIE0
+#endif
+#ifndef RXEN
+#define RXEN    RXEN0
+#endif
+#ifndef TXEN
+#define TXEN    TXEN0
+#endif
+
+/* Some ATC90CAN128 SFR names are different to ATMEGA128. Define some
+   compatibilty macros. */
+#if defined(__AVR_AT90CAN128__) || defined(__AVR_ATmega2561__)
+#ifndef ADCW
+#define ADCW    ADC
+#endif
+#ifndef ADCSR
+#define ADCSR   ADCSRA
+#endif
+#ifndef ADFR
+#define ADFR    ADATE
+#endif
+#ifndef OCIE0
+#define OCIE0   OCIE0A
+#endif
+#ifndef TCCR0
+#define TCCR0   TCCR0A
+#endif
+#ifndef TCCR2
+#define TCCR2   TCCR2A
+#endif
+#ifndef OCR0
+#define OCR0    OCR0A
+#endif
+#ifndef TIMSK
+#define TIMSK   TIMSK0
+#endif
+#ifndef TIFR
+#define TIFR   TIFR0
+#endif
+#endif /* __AVR_AT90CAN128__ */
+
+
+#endif /* __AVR_ENHANCED__ */
+
+
+#endif /* _ARCH_AVR_H_ */

include/arch/avr/atom.h

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: atom.h,v $
+ * Revision 1.2  2005/07/26 15:47:06  haraldkipp
+ * AtomicInc() and AtomicDec() are no longer required by Nut/Net.
+ * Removed to simplify the porting job. Broken applications should
+ * implement their own version.
+ *
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.1  2005/05/27 17:41:52  drsung
+ * Moved the file.
+ *
+ * Revision 1.1  2005/05/26 10:08:42  drsung
+ * Moved the platform dependend code from include/sys/atom.h to this file.
+ *
+ *
+ */
+ 
+#ifndef _SYS_ATOM_H_
+#error "Do not include this file directly. Use sys/atom.h instead!"
+#endif
+
+#ifdef __IMAGECRAFT__
+
+#define NutEnterCritical()  \
+{                           \
+    asm("in R0, 0x3F\n"     \
+        "cli\n"             \
+        "push R0\n");       \
+}
+
+#define NutExitCritical()   \
+{                           \
+    asm("pop R0\n"          \
+        "out 0x3F, R0\n");  \
+}
+
+#else
+
+#define NutEnterCritical_nt()               \
+    asm volatile(                           \
+        "in  __tmp_reg__, __SREG__" "\n\t"  \
+        "cli"                       "\n\t"  \
+        "push __tmp_reg__"          "\n\t"  \
+    )
+
+#define NutExitCritical_nt()                \
+    asm volatile(                           \
+        "pop __tmp_reg__"           "\n\t"  \
+        "out __SREG__, __tmp_reg__" "\n\t"  \
+    )
+
+#ifdef NUTTRACER_CRITICAL
+#define NutEnterCritical()                  \
+    NutEnterCritical_nt();                  \
+    TRACE_ADD_ITEM_PC(TRACE_TAG_CRITICAL_ENTER);
+
+#define NutExitCritical()                   \
+    TRACE_ADD_ITEM_PC(TRACE_TAG_CRITICAL_EXIT); \
+    NutExitCritical_nt()
+#else
+#define NutEnterCritical()                  \
+    NutEnterCritical_nt();
+
+#define NutExitCritical()                   \
+    NutExitCritical_nt()
+#endif
+#endif
+
+#define NutJumpOutCritical() NutExitCritical()
+

include/arch/avr/gcc.h

@@ -0,0 +1,166 @@
+#ifndef _ARCH_AVR_GCC_H_
+#define _ARCH_AVR_GCC_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: gcc.h,v $
+ * Revision 1.3  2007/04/12 09:20:34  haraldkipp
+ * Added new register bit names for the ATmega2561.
+ *
+ * Revision 1.2  2006/01/11 08:32:21  hwmaier
+ * Support for avr-libc >= 1.4.x
+ *
+ * Revision 1.1  2005/10/24 10:46:05  haraldkipp
+ * First check in.
+ * Contents taken from avr.h in the parent directory.
+ *
+ */
+
+
+/* ================================================================ */
+/* To be sorted out.                                                */
+/* ================================================================ */
+
+
+#define CONST   const
+#define INLINE  inline
+
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#if __AVR_LIBC_VERSION__ < 10400UL
+#include <avr/signal.h>
+#endif
+#include <avr/eeprom.h>
+#include <avr/pgmspace.h>
+#include <avr/sleep.h>
+#include <stdlib.h>
+
+
+/*
+ * test for a macro added in avr-libc 1.2.0, if yes use different path for twi.h
+ * note: has to be after #include <eeprom.h>
+ */
+#ifdef eeprom_rb
+#include <avr/twi.h>
+#else
+#include <compat/twi.h>
+#endif
+
+#if defined(__AVR_ATmega2561__)
+#if !defined(TXC)
+#define TXC     TXC0
+#endif
+#if !defined(TXB8)
+#define TXB8     TXB80
+#endif
+#if !defined(UMSEL)
+#define UMSEL     UMSEL00
+#endif
+#if !defined(U2X)
+#define U2X     U2X0
+#endif
+#if !defined(UCSZ0)
+#define UCSZ0     UCSZ00
+#endif
+#if !defined(UCSZ1)
+#define UCSZ1     UCSZ01
+#endif
+#if !defined(UCSZ2)
+#define UCSZ2     UCSZ02
+#endif
+#if !defined(UPM0)
+#define UPM0     UPM00
+#endif
+#if !defined(UPM1)
+#define UPM1     UPM01
+#endif
+
+#if !defined(USBS)
+#define USBS     USBS0
+#endif
+#if !defined(UPE)
+#define UPE     UPE0
+#endif
+#if !defined(MPCM)
+#define MPCM     MPCM0
+#endif
+#if !defined(UCPOL)
+#define UCPOL     UCPOL0
+#endif
+#endif
+
+#ifndef __SFR_OFFSET
+#define __SFR_OFFSET    0
+#endif
+
+#define COMPRESS_DISABLE
+#define COMPRESS_REENABLE
+
+#ifndef _NOP
+#define _NOP() __asm__ __volatile__ ("nop")
+#endif
+
+#ifndef atof
+#define atof(s)	    strtod(s, 0)
+#endif
+
+#define EEPROMReadBytes(addr, ptr, size)    eeprom_read_block((char *)(addr), ptr, size)
+/*!
+ * \brief Read multibyte types from the EEPROM.
+ */
+#define EEPROM_READ(addr, dst)		    eeprom_read_block((char *)(addr), &dst, sizeof(dst))
+#define EEPROMread(addr)	 	    eeprom_read_byte((char *)(addr))
+
+/*!
+ * \brief Write multibyte types to the EEPROM.
+ */
+#define EEPROM_WRITE(addr, src)							\
+{										\
+    unsigned short __i;								\
+    for(__i = 0; __i < sizeof(src); __i++)					\
+	eeprom_write_byte(((char *)(addr)) + __i, *(((char *)(&(src))) + __i)); \
+}
+
+#define EEPROMWriteBytes(addr, ptr, size)					\
+{										\
+    unsigned short __i;								\
+    for(__i = 0; __i < size; __i++)						\
+	eeprom_write_byte(((char *)(addr)) + __i, *(((char *)(ptr)) + __i));	\
+}
+
+#define main    NutAppMain
+
+#endif /* _ARCH_AVR_GCC_H_ */
+

include/arch/avr/icc.h

@@ -0,0 +1,411 @@
+#ifndef _ARCH_AVR_ICC_H_
+#define _ARCH_AVR_ICC_H_
+/*
+ * <MFS> Modified for Streamit
+ * 1) add strstr_P(x,y) define for ICC
+ * 2) swap arguments of 'strncmp_P' function for ICC
+ * 3) create Mega2561 specific Watchdog routines for ICC
+ *
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: icc.h,v $
+ * Revision 1.6  2006/09/29 12:22:07  haraldkipp
+ * Corrected internal RAM size and check compiler environment for ATmega2561.
+ *
+ * Revision 1.5  2006/07/10 08:48:03  haraldkipp
+ * Distinguish between enhanced and extended AVR.
+ *
+ * Revision 1.4  2006/05/25 09:35:27  haraldkipp
+ * Dummy macros added to support the avr-libc special function register
+ * definitions.
+ *
+ * Revision 1.3  2006/02/08 15:20:56  haraldkipp
+ * ATmega2561 Support
+ *
+ * Revision 1.2  2005/10/24 18:04:25  haraldkipp
+ * Duplicate macro definitions removed.
+ * Parameter order of cstrcmp() corrected.
+ * Generic port and flag names added for ATmega103 support.
+ *
+ * Revision 1.1  2005/10/24 10:46:05  haraldkipp
+ * First check in.
+ * Contents taken from avr.h in the parent directory.
+ *
+ */
+
+/*
+ * Include some basic header files of the ImageCraft runtime library.
+ */
+#include <stddef.h>
+#include <macros.h>
+#include <eeprom.h>
+
+/*!
+ * \brief Specify enhanced AVR target.
+ *
+ * For backward compatibility this macro is automatically defined if 
+ * _MCU_enhanced is defined.
+ *
+ */
+#if defined(_MCU_enhanced) || defined(_MCU_extended)
+#undef __AVR_ENHANCED__
+#define __AVR_ENHANCED__ /* Generic test for enhanced AVRs like ATMEGA128, AT09CAN128 */
+#endif
+
+/*!
+ * \brief Disable const keyword.
+ *
+ * ICCAVR doesn't allow to mark function parameters unmodifable
+ * by the 'const' modifier. Even worse, the compiler redefines
+ * the meaning as a program memory attribute.
+ */
+#ifndef CONST
+#define CONST
+#endif
+
+/*!
+ * \brief Disable inline keyword.
+ *
+ * ICCAVR doesn't allow to explicitly mark a function for inline
+ * code generation.
+ */
+#ifndef INLINE
+#define INLINE
+#endif
+
+/*!
+ * \brief Redefined standard library routines.
+ *
+ * ImageCraft has a multipass linker, which is fine for complicated 
+ * dependencies in most cases. However, there is the potential risk,
+ * that standard library calls with the same name are linked from
+ * the wrong library. To avoid this, an additional postfix is added
+ * to routines, which are implemented in Nut/OS libraries.
+ */
+#define printf      printf_M
+#define puts        puts_M
+#define sprintf     sprintf_M
+#define vprintf     vprintf_M
+#define scanf       scanf_M
+#define gets        gets_M
+#define malloc      malloc_M
+#define free        free_M
+
+/*!
+ * \brief Redirected stdio routines.
+ *
+ * Native stdio routines with format strings in program space are
+ * redirected to their Nut/OS implementation.
+ */
+#define cprintf     printf_P
+#define csprintf    sprintf_P
+#define cscanf      scanf_P
+#define csscanf     sscanf_P
+
+#define memcpy_P(dst, src_P, n) cmemcpy(dst, src_P, n)
+#define strcat_P(s1, s2_P)      cstrcat(s1, s2_P)
+
+/*
+ *  PragmaLab: swap arguments for ICC-compare functions.  
+ *             GCC has const par as second argument, while ICC has
+ *             the const par as the first argument
+ */
+#define strcmp_P(s1_P, s2)      cstrcmp(s2, s1_P)   /* Thanks to Michael. */
+
+#define strlen_P(s_P)           cstrlen(s_P)
+#define strncat_P(s1, s2_P, n)  cstrncat(s1, s2_P, n)
+
+/*
+ *  PragmaLab: swap arguments for ICC-compare functions.  
+ *             GCC has const par as second argument, while ICC has
+ *             the const par as the first argument
+ */
+#define strncmp_P(s1_P, s2, n)  cstrncmp(s2, s1_P, n)
+
+
+#define strcpy_P(dst, src_P)    cstrcpy(dst, src_P)
+#define strncpy_P(x,y,z)        cstrncpy(x,y,z)
+// added by PragmaLab dec 2006
+#define strstr_P(x,y)         cstrstr(x,y)
+
+/*!
+ * \brief Case insensitive string comparisions.
+ *
+ * Not supported by ICCAVR and temporarly redirected to
+ * the case sensitive routines.
+ *
+ * \bug Case insensitive string comparisions fail with ICCAVR.
+ */
+#define strcasecmp(s1, s2)  strcmp(s1, s2)
+#define strncasecmp(s1, s2, n)  strncmp(s1, s2, n)
+
+
+/*!
+ * \brief Start of heap area.
+ */
+#define __heap_start   _bss_end
+
+/*!
+ * \brief Object attribute support.
+ *
+ * Not supported by ICCAVR.
+ */
+#define __attribute__(x)
+
+/*!
+ * \brief Declare static pointer to strings in program space.
+ *
+ * No chance with ICCAVR.
+ */
+#define PSTR(p)     (p)
+
+/*! \def PRG_RDB(p)
+ * \brief Read byte from program space.
+ */
+#define PRG_RDB(p)  (*((const char *)(p)))
+
+/*! \def prog_char
+ * \brief Character in program space.
+ */
+#define prog_char const char
+
+/*! \def prog_int
+ * \brief Integer in program space.
+ */
+#define prog_int const int
+
+/*! \def PGM_P
+ * \brief Pointer to character in program space.
+ */
+#define PGM_P prog_char *
+
+
+/* ================================================================ */
+/* PragmaLab 20-02-2007:
+/* For Mega2561 the Watchdog register has moved (0x21 has become 0x60). 
+/* Also clear WDFF bit in MCUSR in disable sequence
+/* ================================================================ */
+
+
+#ifdef ATMega2561
+#define wdt_enable(tmo) \
+{ \
+    register u_char s = _BV(WDCE) | _BV(WDE); \
+    register u_char r = tmo | _BV(WDE); \
+    asm("in R0, 0x3F\n"     \
+        "cli\n"             \
+        "wdr\n"             \
+        "sts 0x60, %s\n"    \
+        "sts 0x60, %r\n"    \
+        "out 0x3F, R0\n");  \
+}
+
+#define wdt_disable() \
+{ \
+        asm("in R0, $3F\n"      \
+        "cli\n"                 \
+        "wdr\n"                 \
+        "in      r24,0x34\n"    \
+        "andi    r24,0xF7\n"    \
+        "out     0x34,r24\n"    \
+        "lds     r24,0x0060\n"  \
+        "ori     r24,0x18\n"    \
+        "sts     0x0060,r24\n"  \
+        "clr     r2\n"          \
+        "sts     0x0060,r2\n"   \
+        "out 0x3F, R0\n");      \
+}
+#else // now for Mega128/103
+
+#define wdt_enable(tmo) \
+{ \
+    register u_char s = _BV(WDCE) | _BV(WDE); \
+    register u_char r = tmo | _BV(WDE); \
+    asm("in R0, 0x3F\n"     \
+        "cli\n"             \
+        "wdr\n"             \
+        "out 0x21, %s\n"    \
+        "out 0x21, %r\n"    \
+        "out 0x3F, R0\n");  \
+}
+
+#define wdt_disable() \
+{ \
+    register u_char s = _BV(WDCE) | _BV(WDE); \
+    register u_char r = 0;  \
+    asm("in R0, $3F\n"      \
+        "cli\n"             \
+        "out 0x21, %s\n"    \
+        "out 0x21, %r\n"    \
+        "out 0x3F, R0\n");  \
+}
+#endif //ATMega2561
+
+#define wdt_reset() \
+{ \
+    _WDR(); \
+}
+
+
+#define __SFR_OFFSET 0
+#define SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET)
+#define SFR_MEM_ADDR(sfr) (sfr)
+#define SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET)
+
+#define _SFR_MEM8(addr)     (addr)
+#define _SFR_MEM16(addr)    (addr)
+
+#define BV(x)       BIT(x)
+#define _BV(x)      BIT(x)
+
+#define cli()           CLI()
+#define sei()           SEI()
+#define cbi(reg, bit)   (reg &= ~BIT(bit))
+#define sbi(reg, bit)   (reg |= BIT(bit))
+
+
+#define loop_until_bit_is_set(reg, bit) while((reg & BIT(bit)) == 0)
+
+#define bit_is_clear(reg, bit)  ((reg & BIT(bit)) == 0)
+#define bit_is_set(reg, bit)    ((reg & BIT(bit)) != 0)
+
+/* FIXME */
+#define parity_even_bit(x)  (0)
+
+/* FIXME */
+#define SIGNAL(x)   void x(void)
+
+#define outp(val, reg)  (reg = val)
+#define outb(reg, val)  (reg = val)
+
+#define inp(reg)        (reg)
+#define inb(reg)        (reg)
+
+#include <eeprom.h>
+
+#if defined(_MCU_enhanced) || defined(_MCU_extended)
+
+#ifdef ATMega2561
+#include <iom2561v.h>
+#define __AVR_ATmega2561__
+#ifndef _EE_EXTIO
+#error "Looks like wrong platform. Select avrext-icc, not avr-icc."
+#endif
+#else
+#include <iom128v.h>
+#define __AVR_ATmega128__
+#endif
+
+#ifndef RAMEND
+#ifdef ATMega2561
+#define RAMEND  0x21FF
+#else
+#define RAMEND  0x10FF
+#endif
+#endif
+
+#ifndef SRW
+#define SRW  6
+#endif
+
+/* ICC doesn't define generic ports and flags. */
+#ifndef TXC
+#define TXC     TXC0
+#endif
+#ifndef ADCSR
+#define ADCSR   ADCSRA
+#endif
+
+/* Master */
+#define TW_START		    0x08
+#define TW_REP_START		0x10
+/* Master Transmitter */
+#define TW_MT_SLA_ACK		0x18
+#define TW_MT_SLA_NACK		0x20
+#define TW_MT_DATA_ACK		0x28
+#define TW_MT_DATA_NACK		0x30
+#define TW_MT_ARB_LOST      0x38
+/* Master Receiver */
+#define TW_MR_ARB_LOST      0x38
+#define TW_MR_SLA_ACK		0x40
+#define TW_MR_SLA_NACK		0x48
+#define TW_MR_DATA_ACK		0x50
+#define TW_MR_DATA_NACK		0x58
+/* Slave Transmitter */
+#define TW_ST_SLA_ACK		0xA8
+#define TW_ST_ARB_LOST_SLA_ACK	0xB0
+#define TW_ST_DATA_ACK		0xB8
+#define TW_ST_DATA_NACK		0xC0
+#define TW_ST_LAST_DATA		0xC8
+/* Slave Receiver */
+#define TW_SR_SLA_ACK		0x60
+#define TW_SR_ARB_LOST_SLA_ACK	0x68
+#define TW_SR_GCALL_ACK		0x70
+#define TW_SR_ARB_LOST_GCALL_ACK 0x78
+#define TW_SR_DATA_ACK		0x80
+#define TW_SR_DATA_NACK		0x88
+#define TW_SR_GCALL_DATA_ACK	0x90
+#define TW_SR_GCALL_DATA_NACK	0x98
+#define TW_SR_STOP		0xA0
+/* Misc */
+#define TW_NO_INFO		0xF8
+#define TW_BUS_ERROR		0x00
+
+
+#else                           /* ATmega103 */
+
+#include <iom103v.h>
+#define __AVR_ATmega103__
+
+#ifndef DOR
+#define DOR  OVR
+#endif
+
+#ifndef RAMEND
+#define RAMEND  0x0FFF
+#endif
+
+#ifndef WDCE
+#define WDCE    WDTOE
+#endif
+
+#endif
+
+#define eeprom_read_block(dst, addr, size)  EEPROMReadBytes((int)addr, dst, size)
+#define eeprom_write_byte(addr, src)        EEPROMwrite((int)addr, src)
+#define eeprom_read_byte(addr)              EEPROMread((int)addr)
+
+
+#endif /* _ARCH_AVR_ICC_H_ */
+
+

include/arch/avr/irqreg.h

@@ -0,0 +1,127 @@
+#ifndef _DEV_IRQREG_AVR_H_
+#define _DEV_IRQREG_AVR_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: irqreg.h,v $
+ * Revision 1.4  2006/02/08 15:20:56  haraldkipp
+ * ATmega2561 Support
+ *
+ * Revision 1.3  2005/10/07 21:52:31  hwmaier
+ * Removed test for __ATmega64__
+ *
+ * Revision 1.2  2005/10/04 05:24:24  hwmaier
+ * Updated interrupt hooks to reflect new CAN interrupt names of avr-lib 1.2.3
+ *
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ * Revision 1.2  2005/02/10 07:06:51  hwmaier
+ * Changes to incorporate support for AT90CAN128 CPU
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ *
+ */
+
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_INTERRUPT2;
+extern IRQ_HANDLER sig_INTERRUPT3;
+extern IRQ_HANDLER sig_INTERRUPT4;
+extern IRQ_HANDLER sig_INTERRUPT5;
+extern IRQ_HANDLER sig_INTERRUPT6;
+extern IRQ_HANDLER sig_INTERRUPT7;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE2;
+extern IRQ_HANDLER sig_OVERFLOW2;
+extern IRQ_HANDLER sig_INPUT_CAPTURE1;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1B;
+extern IRQ_HANDLER sig_OVERFLOW1;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE0;
+extern IRQ_HANDLER sig_OVERFLOW0;
+extern IRQ_HANDLER sig_SPI;
+extern IRQ_HANDLER sig_UART0_TRANS;
+extern IRQ_HANDLER sig_UART0_DATA;
+extern IRQ_HANDLER sig_UART0_RECV;
+extern IRQ_HANDLER sig_ADC;
+extern IRQ_HANDLER sig_EEPROM_READY;
+extern IRQ_HANDLER sig_COMPARATOR;
+
+#if defined(__AVR_AT90CAN128__) || defined(__AVR_ATmega128__) || defined(__AVR_ATmega2561__)
+#define sig_USART0_RECV sig_UART0_RECV
+#define sig_USART0_DATA sig_UART0_DATA
+#define sig_USART0_TRANS sig_UART0_TRANS
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1C;
+extern IRQ_HANDLER sig_INPUT_CAPTURE3;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3B;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3C;
+extern IRQ_HANDLER sig_OVERFLOW3;
+extern IRQ_HANDLER sig_UART1_RECV;
+extern IRQ_HANDLER sig_UART1_DATA;
+extern IRQ_HANDLER sig_UART1_TRANS;
+#define sig_USART1_RECV sig_UART1_RECV
+#define sig_USART1_DATA sig_UART1_DATA
+#define sig_USART1_TRANS sig_UART1_TRANS
+extern IRQ_HANDLER sig_2WIRE_SERIAL;
+extern IRQ_HANDLER sig_SPM_READY;
+#endif
+
+#if defined(__AVR_AT90CAN128__)
+extern IRQ_HANDLER sig_CAN_TRANSFER;
+extern IRQ_HANDLER sig_CAN_OVERRUN;
+#endif
+
+#if defined(__AVR_ATmega2561__)
+extern IRQ_HANDLER sig_PIN_CHANGE0;
+extern IRQ_HANDLER sig_PIN_CHANGE1;
+extern IRQ_HANDLER sig_WATCHDOG_TIMEOUT;
+#define sig_OUTPUT_COMPARE2A sig_OUTPUT_COMPARE2
+extern IRQ_HANDLER sig_OUTPUT_COMPARE2B;
+#define sig_OUTPUT_COMPARE0A sig_OUTPUT_COMPARE0
+extern IRQ_HANDLER sig_OUTPUT_COMPARE0B;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE4A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE4B;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE4C;
+extern IRQ_HANDLER sig_OVERFLOW4;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE5A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE5B;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE5C;
+extern IRQ_HANDLER sig_OVERFLOW5;
+
+#endif
+
+#endif

include/arch/avr/timer.h

@@ -0,0 +1,55 @@
+#ifndef _ARCH_AVR_TIMER_H_
+#define _ARCH_AVR_TIMER_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: timer.h,v $
+ * Revision 1.2  2006/02/08 15:20:56  haraldkipp
+ * ATmega2561 Support
+ *
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ */
+
+#if defined(MCU_AT90CAN128) || defined(MCU_ATMEGA2561)
+#define NutEnableTimerIrq()     sbi(TIMSK2, OCIE2A)
+#define NutDisableTimerIrq()    cbi(TIMSK2, OCIE2A)
+#else
+#define NutEnableTimerIrq()     sbi(TIMSK, OCIE0)
+#define NutDisableTimerIrq()    cbi(TIMSK, OCIE0)
+#endif
+
+#endif
+

include/arch/h8.h

@@ -0,0 +1,93 @@
+#ifndef _ARCH_H8_H_
+#define _ARCH_H8_H_
+
+/*
+ * Copyright (C) 2004 by Jan Dubiec. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JAN DUBIEC AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JAN DUBIEC
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $Log: h8.h,v $
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ */
+
+/*
+ * GCC for H8 microcontrolles defines following macros:
+ *      __H8300H__ when -mh switch is specified in the command line,
+ *      __H8300S__ when -ms switch is specified in the command line,
+ *      __H8300__ when none of above switches is specified.
+ *
+ */
+
+#if !defined(__H8300H__) && !defined(__H8300S__)
+#error "Nut/OS currently runs only on H8/300H or H8S microcontrollers."
+#endif
+
+/* H8/300 is big endian core */
+#if !defined(__BIG_ENDIAN__)
+#define __BIG_ENDIAN__
+#endif
+
+#include <dev/mweeprom.h>
+
+#define CONST      const
+#define INLINE     inline
+
+#define PSTR(p)    (p)
+#define PRG_RDB(p) (*((const char *)(p)))
+
+#define prog_char  const char
+#define PGM_P      prog_char *
+
+#define SIGNAL(x)  __attribute__((interrupt_handler)) void x(void)
+
+#define main       NutAppMain
+
+#define strlen_P(x)             strlen(x)
+#define strcpy_P(x,y)           strcpy(x,y)
+#define strcmp_P(x, y)          strcmp(x, y)
+#define memcpy_P(x, y, z)       memcpy(x, y, z)
+#define fputs_P(x, y)           fputs(x, y)
+#define fprintf_P               fprintf
+
+/*!
+ * \brief End of uninitialised data segment. Defined in the linker script.
+ */
+extern void *__bss_end;
+
+/*!
+ * \brief Begin of the stack segment. Defined in the linker script.
+ */
+extern void *__stack;
+
+#define RAMSTART    ((void *)0xffbf20)
+
+/* #define RAMEND  (0xffbf20 + 0x4000) */
+
+#endif                          /* #ifndef _CPU_H8_H_ */

include/arch/h8300h/atom.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: atom.h,v $
+ * Revision 1.2  2005/07/26 15:47:06  haraldkipp
+ * AtomicInc() and AtomicDec() are no longer required by Nut/Net.
+ * Removed to simplify the porting job. Broken applications should
+ * implement their own version.
+ *
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.1  2005/05/27 17:41:52  drsung
+ * Moved the file.
+ *
+ * Revision 1.1  2005/05/26 10:08:42  drsung
+ * Moved the platform dependend code from include/sys/atom.h to this file.
+ *
+ *
+ */
+
+#ifndef _SYS_ATOM_H_
+#error "Do not include this file directly. Use sys/atom.h instead!"
+#endif
+
+#define NutEnterCritical()                     \
+    {                                          \
+        u_char __ccr__;                        \
+        asm volatile(                          \
+            "stc.b ccr, %0l"            "\n\t" \
+            "orc.b #0xc0, ccr":"=r"(__ccr__):  \
+        );
+
+#define NutExitCritical()                      \
+       asm volatile(                           \
+        "ldc.b %0l, ccr"::"r"(__ccr__)         \
+       );                                      \
+    }
+
+#define NutJumpOutCritical()                   \
+       asm volatile(                           \
+        "ldc.b %0l, ccr"::"r"(__ccr__)         \
+       );
+
+#define NutEnableInt(ccr)                      \
+    {                                          \
+        u_char __ccr__;                        \
+        asm volatile(                          \
+            "stc.b ccr, %0l"            "\n\t" \
+            "andc.b #0x3f, ccr":"=r"(__ccr__): \
+        );
+
+#define NutDisableInt() NutExitCritical()

include/arch/h8300h/h83068f.h

@@ -0,0 +1,1229 @@
+#ifndef __INCLUDE_H83068F_H__
+#define __INCLUDE_H83068F_H__
+
+/*
+ * Copyright (C) 2004 by Jan Dubiec. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JAN DUBIEC AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JAN DUBIEC
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is based on 3068s.h which can be freely downloaded from
+ * http://www.renesas.com/eng/products/mpumcu/tool/crosstool/iodef/index.html.
+ * 
+ * I have added lacking definition of ADRCR register in structure st_bsc
+ * (bus controler), chanded "int" to "short" in some places in order to make
+ * structs/unions be compatible with gcc's "-mint32" option and added appropriate
+ * ifdefs in order to avoid including the contents of this file more than once.
+ *
+ * Jan Dubiec <jdx@slackware.pl>
+ *
+ */
+
+/*
+ * $Log: h83068f.h,v $
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.2  2004/03/19 18:21:12  jdubiec
+ * Added comment about the origin of this file.
+ *
+ * Revision 1.1  2004/03/16 16:48:26  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ */
+
+/************************************************************************/
+/*      H8/3068 Series Include File                        Ver 2.0      */
+/************************************************************************/
+
+union un_p1dr {                 /* union P1DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p2pcr {                /* union P2PCR  */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p2dr {                 /* union P2DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p3dr {                 /* union P3DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p4pcr {                /* union P4PCR  */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p4dr {                 /* union P4DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p5pcr {                /* union P5PCR  */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:4;        /*              */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p5dr {                 /* union P5DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:4;        /*              */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p6dr {                 /* union P6DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p7dr {                 /* union P7DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p8dr {                 /* union P8DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:3;        /*              */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_p9dr {                 /* union P9DR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:2;        /*              */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_padr {                 /* union PADR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_pbdr {                 /* union PBDR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char B7:1;     /*    Bit 7     */
+        unsigned char B6:1;     /*    Bit 6     */
+        unsigned char B5:1;     /*    Bit 5     */
+        unsigned char B4:1;     /*    Bit 4     */
+        unsigned char B3:1;     /*    Bit 3     */
+        unsigned char B2:1;     /*    Bit 2     */
+        unsigned char B1:1;     /*    Bit 1     */
+        unsigned char B0:1;     /*    Bit 0     */
+    } BIT;                      /*              */
+};                              /*              */
+union un_mdcr {                 /* union MDCR   */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:5;        /*              */
+        unsigned char MDS:3;    /*    MDS       */
+    } BIT;                      /*              */
+};                              /*              */
+union un_syscr {                /* union SYSCR  */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char SSBY:1;   /*    SSBY      */
+        unsigned char STS:3;    /*    STS       */
+        unsigned char UE:1;     /*    UE        */
+        unsigned char NMIEG:1;  /*    NMIEG     */
+        unsigned char SSOE:1;   /*    SSOE      */
+        unsigned char RAME:1;   /*    RAME      */
+    } BIT;                      /*              */
+};                              /*              */
+union un_divcr {                /* union DIVCR  */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:6;        /*              */
+        unsigned char DIV:2;    /*    DIV       */
+    } BIT;                      /*              */
+};                              /*              */
+union un_mstcr {                /* union MSTCR  */
+    unsigned short WORD;        /*  Word Access */
+    struct {                    /*  Byte Access */
+        unsigned char H;        /*    High      */
+        unsigned char L;        /*    Low       */
+    } BYTE;                     /*              */
+    struct {                    /*  Bit  Access */
+        unsigned char PSTOP:1;  /*    PSTOP     */
+        unsigned char:4;        /*              */
+        unsigned char _SCI2:1;  /*    MSTPH2    */
+        unsigned char _SCI1:1;  /*    MSTPH1    */
+        unsigned char _SCI0:1;  /*    MSTPH0    */
+        unsigned char _DMAC:1;  /*    MSTPL7    */
+        unsigned char:1;        /*              */
+        unsigned char _DRAM:1;  /*    MSTPL5    */
+        unsigned char _ITU:1;   /*    MSTPL4    */
+        unsigned char _TMR01:1; /*    MSTPL3    */
+        unsigned char _TMR23:1; /*    MSTPL2    */
+        unsigned char:1;        /*              */
+        unsigned char _AD:1;    /*    MSTPL0    */
+    } BIT;                      /*              */
+};                              /*              */
+struct st_bsc {                 /* struct BSC   */
+    char wk1;                   /*              */
+    union {                     /* BRCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char A23E:1;       /*    A23E      */
+            unsigned char A22E:1;       /*    A22E      */
+            unsigned char A21E:1;       /*    A21E      */
+            unsigned char A20E:1;       /*    A20E      */
+            unsigned char:3;    /*              */
+            unsigned char BRLE:1;       /*    BRLE      */
+        } BIT;                  /*              */
+    } BRCR;                     /*              */
+    char wk2[10];               /*              */
+    union {                     /* ADRCR        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:7;    /*              */
+            unsigned char ADRCTL:1;     /*    ADRCTL    */
+        } BIT;                  /*              */
+    } ADRCR;                    /*              */
+    union {                     /* CSCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CS7E:1;       /*    CS7E      */
+            unsigned char CS6E:1;       /*    CS6E      */
+            unsigned char CS5E:1;       /*    CS5E      */
+            unsigned char CS4E:1;       /*    CS4E      */
+        } BIT;                  /*              */
+    } CSCR;                     /*              */
+    union {                     /* ABWCR        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char ABW7:1;       /*    ABW7      */
+            unsigned char ABW6:1;       /*    ABW6      */
+            unsigned char ABW5:1;       /*    ABW5      */
+            unsigned char ABW4:1;       /*    ABW4      */
+            unsigned char ABW3:1;       /*    ABW3      */
+            unsigned char ABW2:1;       /*    ABW2      */
+            unsigned char ABW1:1;       /*    ABW1      */
+            unsigned char ABW0:1;       /*    ABW0      */
+        } BIT;                  /*              */
+    } ABWCR;                    /*              */
+    union {                     /* ASTCR        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char AST7:1;       /*    AST7      */
+            unsigned char AST6:1;       /*    AST6      */
+            unsigned char AST5:1;       /*    AST5      */
+            unsigned char AST4:1;       /*    AST4      */
+            unsigned char AST3:1;       /*    AST3      */
+            unsigned char AST2:1;       /*    AST2      */
+            unsigned char AST1:1;       /*    AST1      */
+            unsigned char AST0:1;       /*    AST0      */
+        } BIT;                  /*              */
+    } ASTCR;                    /*              */
+    union {                     /* WCR          */
+        unsigned short WORD;    /*  Word Access */
+        struct {                /*  Byte Access */
+            unsigned char H;    /*    WCRH      */
+            unsigned char L;    /*    WCRL      */
+        } BYTE;                 /*              */
+        struct {                /*  Bit  Access */
+            unsigned char W7:2; /*    W7        */
+            unsigned char W6:2; /*    W6        */
+            unsigned char W5:2; /*    W5        */
+            unsigned char W4:2; /*    W4        */
+            unsigned char W3:2; /*    W3        */
+            unsigned char W2:2; /*    W2        */
+            unsigned char W1:2; /*    W1        */
+            unsigned char W0:2; /*    W0        */
+        } BIT;                  /*              */
+    } WCR;                      /*              */
+    union {                     /* BCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char ICIS1:1;      /*    ICIS1     */
+            unsigned char ICIS0:1;      /*    ICIS0     */
+            unsigned char BROME:1;      /*    BROME     */
+            unsigned char BRSTS1:1;     /*    BRSTS1    */
+            unsigned char BRSTS0:1;     /*    BRSTS0    */
+            unsigned char:1;    /*              */
+            unsigned char RDEA:1;       /*    RDEA      */
+            unsigned char WAITE:1;      /*    WAITE     */
+        } BIT;                  /*              */
+    } BCR;                      /*              */
+    char wk3;                   /*              */
+    union {                     /* DRCRA        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DRAS:3;       /*    DRAS      */
+            unsigned char:1;    /*              */
+            unsigned char BE:1; /*    BE        */
+            unsigned char RDM:1;        /*    RDM       */
+            unsigned char SRFMD:1;      /*    SRFMD     */
+            unsigned char RFSHE:1;      /*    RFSHE     */
+        } BIT;                  /*              */
+    } DRCRA;                    /*              */
+    union {                     /* DRCRB        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char MXC:2;        /*    MXC       */
+            unsigned char CSEL:1;       /*    CSEL      */
+            unsigned char RCYCE:1;      /*    RCYCE     */
+            unsigned char:1;    /*              */
+            unsigned char _TPC:1;       /*    TPC       */
+            unsigned char RCW:1;        /*    RCW       */
+            unsigned char RLW:1;        /*    RLW       */
+        } BIT;                  /*              */
+    } DRCRB;                    /*              */
+    union {                     /* RTMCSR       */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMF:1;        /*    CMF       */
+            unsigned char CMIE:1;       /*    CMIE      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } RTMCSR;                   /*              */
+    unsigned char RTCNT;        /* RTCNT        */
+    unsigned char RTCOR;        /* RTCOR        */
+};                              /*              */
+struct st_intc {                /* struct INTC  */
+    union {                     /* ISCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:2;    /*              */
+            unsigned char IRQ5SC:1;     /*    IRQ5SC    */
+            unsigned char IRQ4SC:1;     /*    IRQ4SC    */
+            unsigned char IRQ3SC:1;     /*    IRQ3SC    */
+            unsigned char IRQ2SC:1;     /*    IRQ2SC    */
+            unsigned char IRQ1SC:1;     /*    IRQ1SC    */
+            unsigned char IRQ0SC:1;     /*    IRQ0SC    */
+        } BIT;                  /*              */
+    } ISCR;                     /*              */
+    union {                     /* IER          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:2;    /*              */
+            unsigned char IRQ5E:1;      /*    IRQ5E     */
+            unsigned char IRQ4E:1;      /*    IRQ4E     */
+            unsigned char IRQ3E:1;      /*    IRQ3E     */
+            unsigned char IRQ2E:1;      /*    IRQ2E     */
+            unsigned char IRQ1E:1;      /*    IRQ1E     */
+            unsigned char IRQ0E:1;      /*    IRQ0E     */
+        } BIT;                  /*              */
+    } IER;                      /*              */
+    union {                     /* ISR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:2;    /*              */
+            unsigned char IRQ5F:1;      /*    IRQ5F     */
+            unsigned char IRQ4F:1;      /*    IRQ4F     */
+            unsigned char IRQ3F:1;      /*    IRQ3F     */
+            unsigned char IRQ2F:1;      /*    IRQ2F     */
+            unsigned char IRQ1F:1;      /*    IRQ1F     */
+            unsigned char IRQ0F:1;      /*    IRQ0F     */
+        } BIT;                  /*              */
+    } ISR;                      /*              */
+    char wk;                    /*              */
+    union {                     /* IPRA         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char _IRQ0:1;      /*    IRQ0      */
+            unsigned char _IRQ1:1;      /*    IRQ1      */
+            unsigned char _IRQ23:1;     /*    IRQ2,IRQ3 */
+            unsigned char _IRQ45:1;     /*    IRQ4,IRQ5 */
+            unsigned char _WDT:1;       /* WDT,DRAM,A/D */
+            unsigned char _ITU0:1;      /*    ITU0      */
+            unsigned char _ITU1:1;      /*    ITU1      */
+            unsigned char _ITU2:1;      /*    ITU2      */
+        } BIT;                  /*              */
+    } IPRA;                     /*              */
+    union {                     /* IPRB         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char _TMR01:1;     /*    TMR0,1    */
+            unsigned char _TMR23:1;     /*    TMR2,3    */
+            unsigned char _DMAC:1;      /*    DMAC      */
+            unsigned char:1;    /*              */
+            unsigned char _SCI0:1;      /*    SCI0      */
+            unsigned char _SCI1:1;      /*    SCI1      */
+            unsigned char _SCI2:1;      /*    SCI2      */
+        } BIT;                  /*              */
+    } IPRB;                     /*              */
+};                              /*              */
+#if __CPU__==2                  /* Normal Mode  */
+struct st_sam {                 /* struct DMAC  */
+    char wk[2];                 /*              */
+    void *MAR;                  /* MAR          */
+    unsigned short ETCR;        /* ETCR         */
+    unsigned char IOAR;         /* IOAR         */
+    union {                     /* DTCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTE:1;        /*    DTE       */
+            unsigned char DTSZ:1;       /*    DTSZ      */
+            unsigned char DTID:1;       /*    DTID      */
+            unsigned char RPE:1;        /*    RPE       */
+            unsigned char DTIE:1;       /*    DTIE      */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCR;                     /*              */
+};                              /*              */
+struct st_fam {                 /* struct DMAC  */
+    char wk1[2];                /*              */
+    void *MARA;                 /* MARA         */
+    unsigned short ETCRA;       /* ETCRA        */
+    char wk2;                   /*              */
+    union {                     /* DTCRA        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTE:1;        /*    DTE       */
+            unsigned char DTSZ:1;       /*    DTSZ      */
+            unsigned char SAID:1;       /*    SAID      */
+            unsigned char SAIDE:1;      /*    SAIDE     */
+            unsigned char DTIE:1;       /*    DTIE      */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCRA;                    /*              */
+    char wk3[2];                /*              */
+    void *MARB;                 /* MARB         */
+    unsigned short ETCRB;       /* ETCRB        */
+    char wk4;                   /*              */
+    union {                     /* DTCRB        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTME:1;       /*    DTME      */
+            unsigned char:1;    /*              */
+            unsigned char DAID:1;       /*    DAID      */
+            unsigned char DAIDE:1;      /*    DAIDE     */
+            unsigned char TMS:1;        /*    TMS       */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCRB;                    /*              */
+};                              /*              */
+#else                           /* Advanced Mode */
+struct st_sam {                 /* struct DMAC  */
+    void *MAR;                  /* MAR          */
+    unsigned short ETCR;        /* ETCR         */
+    unsigned char IOAR;         /* IOAR         */
+    union {                     /* DTCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTE:1;        /*    DTE       */
+            unsigned char DTSZ:1;       /*    DTSZ      */
+            unsigned char DTID:1;       /*    DTID      */
+            unsigned char RPE:1;        /*    RPE       */
+            unsigned char DTIE:1;       /*    DTIE      */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCR;                     /*              */
+};                              /*              */
+struct st_fam {                 /* struct DMAC  */
+    void *MARA;                 /* MARA         */
+    unsigned short ETCRA;       /* ETCRA        */
+    char wk1;                   /*              */
+    union {                     /* DTCRA        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTE:1;        /*    DTE       */
+            unsigned char DTSZ:1;       /*    DTSZ      */
+            unsigned char SAID:1;       /*    SAID      */
+            unsigned char SAIDE:1;      /*    SAIDE     */
+            unsigned char DTIE:1;       /*    DTIE      */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCRA;                    /*              */
+    void *MARB;                 /* MARB         */
+    unsigned short ETCRB;       /* ETCRB        */
+    char wk2;                   /*              */
+    union {                     /* DTCRB        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DTME:1;       /*    DTME      */
+            unsigned char:1;    /*              */
+            unsigned char DAID:1;       /*    DAID      */
+            unsigned char DAIDE:1;      /*    DAIDE     */
+            unsigned char TMS:1;        /*    TMS       */
+            unsigned char DTS:3;        /*    DTS       */
+        } BIT;                  /*              */
+    } DTCRB;                    /*              */
+};                              /*              */
+#endif                          /*              */
+struct st_flash {               /* struct FLASH */
+    union {                     /* FLMCR1       */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char FWE:1;        /*    FWE       */
+            unsigned char SWE:1;        /*    SWE       */
+            unsigned char ESU:1;        /*    ESU       */
+            unsigned char PSU:1;        /*    PSU       */
+            unsigned char EV:1; /*    EV        */
+            unsigned char PV:1; /*    PV        */
+            unsigned char E:1;  /*    E         */
+            unsigned char P:1;  /*    P         */
+        } BIT;                  /*              */
+    } FLMCR1;                   /*              */
+    union {                     /* FLMCR2       */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char FLER:1;       /*    FLER      */
+        } BIT;                  /*              */
+    } FLMCR2;                   /*              */
+    union {                     /* EBR1         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char EB7:1;        /*    EB7       */
+            unsigned char EB6:1;        /*    EB6       */
+            unsigned char EB5:1;        /*    EB5       */
+            unsigned char EB4:1;        /*    EB4       */
+            unsigned char EB3:1;        /*    EB3       */
+            unsigned char EB2:1;        /*    EB2       */
+            unsigned char EB1:1;        /*    EB1       */
+            unsigned char EB0:1;        /*    EB0       */
+        } BIT;                  /*              */
+    } EBR1;                     /*              */
+    union {                     /* EBR2         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:2;    /*              */
+            unsigned char EB13:1;       /*    EB13      */
+            unsigned char EB12:1;       /*    EB12      */
+            unsigned char EB11:1;       /*    EB11      */
+            unsigned char EB10:1;       /*    EB10      */
+            unsigned char EB9:1;        /*    EB9       */
+            unsigned char EB8:1;        /*    EB8       */
+        } BIT;                  /*              */
+    } EBR2;                     /*              */
+    char wk[67];                /*              */
+    union {                     /* RAMCR        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char RAMS:1;       /*    RAMS      */
+            unsigned char RAM:3;        /*    RAM       */
+        } BIT;                  /*              */
+    } RAMCR;                    /*              */
+};                              /*              */
+struct st_itu {                 /* struct ITU   */
+    union {                     /* TSTR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:5;    /*              */
+            unsigned char STR2:1;       /*    STR2      */
+            unsigned char STR1:1;       /*    STR1      */
+            unsigned char STR0:1;       /*    STR0      */
+        } BIT;                  /*              */
+    } TSTR;                     /*              */
+    union {                     /* TSNC         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:5;    /*              */
+            unsigned char SYNC2:1;      /*    SYNC2     */
+            unsigned char SYNC1:1;      /*    SYNC1     */
+            unsigned char SYNC0:1;      /*    SYNC0     */
+        } BIT;                  /*              */
+    } TSNC;                     /*              */
+    union {                     /* TMDR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char MDF:1;        /*    MDF       */
+            unsigned char FDIR:1;       /*    FDIR      */
+            unsigned char:2;    /*              */
+            unsigned char PWM2:1;       /*    PWM2      */
+            unsigned char PWM1:1;       /*    PWM1      */
+            unsigned char PWM0:1;       /*    PWM0      */
+        } BIT;                  /*              */
+    } TMDR;                     /*              */
+    union {                     /* TOLR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:2;    /*              */
+            unsigned char TOB2:1;       /*    TOB2      */
+            unsigned char TOA2:1;       /*    TOA2      */
+            unsigned char TOB1:1;       /*    TOB1      */
+            unsigned char TOA1:1;       /*    TOA1      */
+            unsigned char TOB0:1;       /*    TOB0      */
+            unsigned char TOA0:1;       /*    TOA0      */
+        } BIT;                  /*              */
+    } TOLR;                     /*              */
+    union {                     /* TISRA        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char IMIEA2:1;     /*    IMIEA2    */
+            unsigned char IMIEA1:1;     /*    IMIEA2    */
+            unsigned char IMIEA0:1;     /*    IMIEA2    */
+            unsigned char:1;    /*              */
+            unsigned char IMFA2:1;      /*    IMFA2     */
+            unsigned char IMFA1:1;      /*    IMFA1     */
+            unsigned char IMFA0:1;      /*    IMFA0     */
+        } BIT;                  /*              */
+    } TISRA;                    /*              */
+    union {                     /* TISRB        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char IMIEB2:1;     /*    IMIEB2    */
+            unsigned char IMIEB1:1;     /*    IMIEB2    */
+            unsigned char IMIEB0:1;     /*    IMIEB2    */
+            unsigned char:1;    /*              */
+            unsigned char IMFB2:1;      /*    IMFB2     */
+            unsigned char IMFB1:1;      /*    IMFB1     */
+            unsigned char IMFB0:1;      /*    IMFB0     */
+        } BIT;                  /*              */
+    } TISRB;                    /*              */
+    union {                     /* TISRC        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char OVIE2:1;      /*    OVIE2     */
+            unsigned char OVIE1:1;      /*    OVIE2     */
+            unsigned char OVIE0:1;      /*    OVIE2     */
+            unsigned char:1;    /*              */
+            unsigned char OVF2:1;       /*    OVF2      */
+            unsigned char OVF1:1;       /*    OVF1      */
+            unsigned char OVF0:1;       /*    OVF0      */
+        } BIT;                  /*              */
+    } TISRC;                    /*              */
+};                              /*              */
+struct st_itu0 {                /* struct ITU0  */
+    union {                     /* TCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKEG:2;       /*    CKEG      */
+            unsigned char TPSC:3;       /*    TPSC      */
+        } BIT;                  /*              */
+    } TCR;                      /*              */
+    union {                     /* TIOR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:1;    /*              */
+            unsigned char IOB:3;        /*    IOB       */
+            unsigned char:1;    /*              */
+            unsigned char IOA:3;        /*    IOA       */
+        } BIT;                  /*              */
+    } TIOR;                     /*              */
+    unsigned short TCNT;        /* TCNT         */
+    unsigned short GRA;         /* GRA          */
+    unsigned short GRB;         /* GRB          */
+};                              /*              */
+union un_wdt {                  /* union WDT    */
+    struct {                    /* Read  Access */
+        union {                 /* TCSR         */
+            unsigned char BYTE; /*  Byte Access */
+            struct {            /*  Bit  Access */
+                unsigned char OVF:1;    /*    OVF       */
+                unsigned char WTIT:1;   /*    WT/IT     */
+                unsigned char TME:1;    /*    TME       */
+                unsigned char:2;        /*              */
+                unsigned char CKS:3;    /*    CKS       */
+            } BIT;              /*              */
+        } TCSR;                 /*              */
+        unsigned char TCNT;     /* TCNT         */
+        char wk;                /*              */
+        union {                 /* RSTCSR       */
+            unsigned char BYTE; /*  Byte Access */
+            struct {            /*              */
+                unsigned char WRST:1;   /*    WSRT      */
+            } BIT;              /*              */
+        } RSTCSR;               /*              */
+    } READ;                     /*              */
+    struct {                    /* Write Access */
+        unsigned short TCSR;    /* TCSR/TCNT    */
+        unsigned short RSTCSR;  /* RSTCSR       */
+    } WRITE;                    /*              */
+};                              /*              */
+struct st_tmr01 {               /* struct TMR01 */
+    union {                     /* TCR0         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR0;                     /*              */
+    union {                     /* TCR1         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR1;                     /*              */
+    union {                     /* TCSR0        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char ADTE:1;       /*    ADTE      */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR0;                    /*              */
+    union {                     /* TCSR1        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char ICE:1;        /*    ICE       */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR1;                    /*              */
+    unsigned short TCORA;       /* TCORA        */
+    unsigned short TCORB;       /* TCORB        */
+    unsigned short TCNT;        /* TCNT         */
+};                              /*              */
+struct st_tmr23 {               /* struct TMR23 */
+    union {                     /* TCR2         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR2;                     /*              */
+    union {                     /* TCR3         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR3;                     /*              */
+    union {                     /* TCSR2        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char:1;    /*              */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR2;                    /*              */
+    union {                     /* TCSR3        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char ICE:1;        /*    ICE       */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR3;                    /*              */
+    unsigned short TCORA;       /* TCORA        */
+    unsigned short TCORB;       /* TCORB        */
+    unsigned short TCNT;        /* TCNT         */
+};                              /*              */
+struct st_tmr0 {                /* struct TMR0  */
+    union {                     /* TCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR;                      /*              */
+    char wk1;                   /*              */
+    union {                     /* TCSR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char ADTE:1;       /*    ADTE      */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR;                     /*              */
+    char wk2;                   /*              */
+    unsigned char TCORA;        /* TCORA        */
+    char wk3;                   /*              */
+    unsigned char TCORB;        /* TCORB        */
+    char wk4;                   /*              */
+    unsigned char TCNT;         /* TCNT         */
+};                              /*              */
+struct st_tmr1 {                /* struct TMR1  */
+    union {                     /* TCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR;                      /*              */
+    char wk1;                   /*              */
+    union {                     /* TCSR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char ICE:1;        /*    ICE       */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR;                     /*              */
+    char wk2;                   /*              */
+    unsigned char TCORA;        /* TCORA        */
+    char wk3;                   /*              */
+    unsigned char TCORB;        /* TCORB        */
+    char wk4;                   /*              */
+    unsigned char TCNT;         /* TCNT         */
+};                              /*              */
+struct st_tmr2 {                /* struct TMR2  */
+    union {                     /* TCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMIEB:1;      /*    CMIEB     */
+            unsigned char CMIEA:1;      /*    CMIEA     */
+            unsigned char OVIE:1;       /*    OVIE      */
+            unsigned char CCLR:2;       /*    CCLR      */
+            unsigned char CKS:3;        /*    CKS       */
+        } BIT;                  /*              */
+    } TCR;                      /*              */
+    char wk1;                   /*              */
+    union {                     /* TCSR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CMFB:1;       /*    CMFB      */
+            unsigned char CMFA:1;       /*    CMFA      */
+            unsigned char OVF:1;        /*    OVF       */
+            unsigned char:1;    /*              */
+            unsigned char OS:4; /*    OS        */
+        } BIT;                  /*              */
+    } TCSR;                     /*              */
+    char wk2;                   /*              */
+    unsigned char TCORA;        /* TCORA        */
+    char wk3;                   /*              */
+    unsigned char TCORB;        /* TCORB        */
+    char wk4;                   /*              */
+    unsigned char TCNT;         /* TCNT         */
+};                              /*              */
+union un_dastcr {               /* DASTCR       */
+    unsigned char BYTE;         /*  Byte Access */
+    struct {                    /*  Bit  Access */
+        unsigned char:7;        /*              */
+        unsigned char DASTE:1;  /*    DASTE     */
+    } BIT;                      /*              */
+};                              /*              */
+struct st_da {                  /* struct D/A   */
+    unsigned char DADR0;        /* DADR0        */
+    unsigned char DADR1;        /* DADR1        */
+    union {                     /* DACR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char DAOE1:1;      /*    DAOE1     */
+            unsigned char DAOE0:1;      /*    DAOE0     */
+            unsigned char DAE:1;        /*    DAE       */
+        } BIT;                  /*              */
+    } DACR;                     /*              */
+};                              /*              */
+struct st_tpc {                 /* struct TPC   */
+    union {                     /* TPMR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char G3NOV:1;      /*    G3NOV     */
+            unsigned char G2NOV:1;      /*    G2NOV     */
+            unsigned char G1NOV:1;      /*    G1NOV     */
+            unsigned char G0NOV:1;      /*    G0NOV     */
+        } BIT;                  /*              */
+    } TPMR;                     /*              */
+    union {                     /* TPCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char G3CMS:2;      /*    G3CMS     */
+            unsigned char G2CMS:2;      /*    G2CMS     */
+            unsigned char G1CMS:2;      /*    G1CMS     */
+            unsigned char G0CMS:2;      /*    G0CMS     */
+        } BIT;                  /*              */
+    } TPCR;                     /*              */
+    union {                     /* NDERB        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char B15:1;        /*    NDER15    */
+            unsigned char B14:1;        /*    NDER14    */
+            unsigned char B13:1;        /*    NDER13    */
+            unsigned char B12:1;        /*    NDER12    */
+            unsigned char B11:1;        /*    NDER11    */
+            unsigned char B10:1;        /*    NDER10    */
+            unsigned char B9:1; /*    NDER9     */
+            unsigned char B8:1; /*    NDER8     */
+        } BIT;                  /*              */
+    } NDERB;                    /*              */
+    union {                     /* NDERA        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char B7:1; /*    NDER7     */
+            unsigned char B6:1; /*    NDER6     */
+            unsigned char B5:1; /*    NDER5     */
+            unsigned char B4:1; /*    NDER4     */
+            unsigned char B3:1; /*    NDER3     */
+            unsigned char B2:1; /*    NDER2     */
+            unsigned char B1:1; /*    NDER1     */
+            unsigned char B0:1; /*    NDER0     */
+        } BIT;                  /*              */
+    } NDERA;                    /*              */
+    union {                     /* NDRB (H'A4)  */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char B15:1;        /*    NDR15     */
+            unsigned char B14:1;        /*    NDR14     */
+            unsigned char B13:1;        /*    NDR13     */
+            unsigned char B12:1;        /*    NDR12     */
+            unsigned char B11:1;        /*    NDR11     */
+            unsigned char B10:1;        /*    NDR10     */
+            unsigned char B9:1; /*    NDR9      */
+            unsigned char B8:1; /*    NDR8      */
+        } BIT;                  /*              */
+    } NDRB1;                    /*              */
+    union {                     /* NDRA (H'A5)  */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char B7:1; /*    NDR7      */
+            unsigned char B6:1; /*    NDR6      */
+            unsigned char B5:1; /*    NDR5      */
+            unsigned char B4:1; /*    NDR4      */
+            unsigned char B3:1; /*    NDR3      */
+            unsigned char B2:1; /*    NDR2      */
+            unsigned char B1:1; /*    NDR1      */
+            unsigned char B0:1; /*    NDR0      */
+        } BIT;                  /*              */
+    } NDRA1;                    /*              */
+    union {                     /* NDRB (H'A6)  */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char B11:1;        /*    NDR11     */
+            unsigned char B10:1;        /*    NDR10     */
+            unsigned char B9:1; /*    NDR9      */
+            unsigned char B8:1; /*    NDR8      */
+        } BIT;                  /*              */
+    } NDRB2;                    /*              */
+    union {                     /* NDRA (H'A7)  */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char B3:1; /*    NDR3      */
+            unsigned char B2:1; /*    NDR2      */
+            unsigned char B1:1; /*    NDR1      */
+            unsigned char B0:1; /*    NDR0      */
+        } BIT;                  /*              */
+    } NDRA2;                    /*              */
+};                              /*              */
+struct st_sci {                 /* struct SCI   */
+    union {                     /* SMR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char CA:1; /*    C/A       */
+            unsigned char CHR:1;        /*    CHR       */
+            unsigned char PE:1; /*    PE        */
+            unsigned char OE:1; /*    O/E       */
+            unsigned char STOP:1;       /*    STOP      */
+            unsigned char MP:1; /*    MP        */
+            unsigned char CKS:2;        /*    CKS       */
+        } BIT;                  /*              */
+    } SMR;                      /*              */
+    unsigned char BRR;          /* BRR          */
+    union {                     /* SCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char TIE:1;        /*    TIE       */
+            unsigned char RIE:1;        /*    RIE       */
+            unsigned char TE:1; /*    TE        */
+            unsigned char RE:1; /*    RE        */
+            unsigned char MPIE:1;       /*    MPIE      */
+            unsigned char TEIE:1;       /*    TEIE      */
+            unsigned char CKE:2;        /*    CKE       */
+        } BIT;                  /*              */
+    } SCR;                      /*              */
+    unsigned char TDR;          /* TDR          */
+    union {                     /* SSR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char TDRE:1;       /*    TDRE      */
+            unsigned char RDRF:1;       /*    RDRF      */
+            unsigned char ORER:1;       /*    ORER      */
+            unsigned char FER:1;        /*    FER       */
+            unsigned char PER:1;        /*    PER       */
+            unsigned char TEND:1;       /*    TEND      */
+            unsigned char MPB:1;        /*    MPB       */
+            unsigned char MPBT:1;       /*    MPBT      */
+        } BIT;                  /*              */
+    } SSR;                      /*              */
+    unsigned char RDR;          /* RDR          */
+    union {                     /* SCMR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char SDIR:1;       /*    SDIR      */
+            unsigned char SINV:1;       /*    SINV      */
+            unsigned char:1;    /*              */
+            unsigned char SMIF:1;       /*    SMIF      */
+        } BIT;                  /*              */
+    } SCMR;                     /*              */
+};                              /*              */
+struct st_smci {                /* struct SMCI  */
+    union {                     /* SMR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char GM:1; /*    GM        */
+            unsigned char CHR:1;        /*    CHR       */
+            unsigned char PE:1; /*    PE        */
+            unsigned char OE:1; /*    O/E       */
+            unsigned char STOP:1;       /*    STOP      */
+            unsigned char MP:1; /*    MP        */
+            unsigned char CKS:2;        /*    CKS       */
+        } BIT;                  /*              */
+    } SMR;                      /*              */
+    unsigned char BRR;          /* BRR          */
+    union {                     /* SCR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char TIE:1;        /*    TIE       */
+            unsigned char RIE:1;        /*    RIE       */
+            unsigned char TE:1; /*    TE        */
+            unsigned char RE:1; /*    RE        */
+            unsigned char MPIE:1;       /*    MPIE      */
+            unsigned char TEIE:1;       /*    TEIE      */
+            unsigned char CKE:2;        /*    CKE       */
+        } BIT;                  /*              */
+    } SCR;                      /*              */
+    unsigned char TDR;          /* TDR          */
+    union {                     /* SSR          */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char TDRE:1;       /*    TDRE      */
+            unsigned char RDRF:1;       /*    RDRF      */
+            unsigned char ORER:1;       /*    ORER      */
+            unsigned char ERS:1;        /*    ERS       */
+            unsigned char PER:1;        /*    PER       */
+            unsigned char TEND:1;       /*    TEND      */
+            unsigned char MPB:1;        /*    MPB       */
+            unsigned char MPBT:1;       /*    MPBT      */
+        } BIT;                  /*              */
+    } SSR;                      /*              */
+    unsigned char RDR;          /* RDR          */
+    union {                     /* SCMR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char:4;    /*              */
+            unsigned char SDIR:1;       /*    SDIR      */
+            unsigned char SINV:1;       /*    SINV      */
+            unsigned char:1;    /*              */
+            unsigned char SMIF:1;       /*    SMIF      */
+        } BIT;                  /*              */
+    } SCMR;                     /*              */
+};                              /*              */
+struct st_ad {                  /* struct A/D   */
+    unsigned short ADDRA;       /* ADDRA        */
+    unsigned short ADDRB;       /* ADDRB        */
+    unsigned short ADDRC;       /* ADDRC        */
+    unsigned short ADDRD;       /* ADDRD        */
+    union {                     /* ADCSR        */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char ADF:1;        /*    ADF       */
+            unsigned char ADIE:1;       /*    ADIE      */
+            unsigned char ADST:1;       /*    ADST      */
+            unsigned char SCAN:1;       /*    SCAN      */
+            unsigned char CKS:1;        /*    CKS       */
+            unsigned char CH:3; /*    CH        */
+        } BIT;                  /*              */
+    } ADCSR;                    /*              */
+    union {                     /* ADCR         */
+        unsigned char BYTE;     /*  Byte Access */
+        struct {                /*  Bit  Access */
+            unsigned char TRGE:1;       /*    TRGE      */
+        } BIT;                  /*              */
+    } ADCR;                     /*              */
+};                              /*              */
+#define P1DDR   (*(volatile unsigned char   *)0xFEE000) /* P1DDR Address */
+#define P2DDR   (*(volatile unsigned char   *)0xFEE001) /* P2DDR Address */
+#define P3DDR   (*(volatile unsigned char   *)0xFEE002) /* P3DDR Address */
+#define P4DDR   (*(volatile unsigned char   *)0xFEE003) /* P4DDR Address */
+#define P5DDR   (*(volatile unsigned char   *)0xFEE004) /* P5DDR Address */
+#define P6DDR   (*(volatile unsigned char   *)0xFEE005) /* P6DDR Address */
+#define P8DDR   (*(volatile unsigned char   *)0xFEE007) /* P8DDR Address */
+#define P9DDR   (*(volatile unsigned char   *)0xFEE008) /* P9DDR Address */
+#define PADDR   (*(volatile unsigned char   *)0xFEE009) /* PADDR Address */
+#define PBDDR   (*(volatile unsigned char   *)0xFEE00A) /* PBDDR Address */
+#define P2PCR   (*(volatile union  un_p2pcr *)0xFEE03C) /* P2PCR Address */
+#define P4PCR   (*(volatile union  un_p4pcr *)0xFEE03E) /* P4PCR Address */
+#define P5PCR   (*(volatile union  un_p5pcr *)0xFEE03F) /* P5PCR Address */
+#define P1DR    (*(volatile union  un_p1dr  *)0xFFFFD0) /* P1DR  Address */
+#define P2DR    (*(volatile union  un_p2dr  *)0xFFFFD1) /* P2DR  Address */
+#define P3DR    (*(volatile union  un_p3dr  *)0xFFFFD2) /* P3DR  Address */
+#define P4DR    (*(volatile union  un_p4dr  *)0xFFFFD3) /* P4DR  Address */
+#define P5DR    (*(volatile union  un_p5dr  *)0xFFFFD4) /* P5DR  Address */
+#define P6DR    (*(volatile union  un_p6dr  *)0xFFFFD5) /* P6DR  Address */
+#define P7DR    (*(volatile union  un_p7dr  *)0xFFFFD6) /* P7DR  Address */
+#define P8DR    (*(volatile union  un_p8dr  *)0xFFFFD7) /* P8DR  Address */
+#define P9DR    (*(volatile union  un_p9dr  *)0xFFFFD8) /* P9DR  Address */
+#define PADR    (*(volatile union  un_padr  *)0xFFFFD9) /* PADR  Address */
+#define PBDR    (*(volatile union  un_pbdr  *)0xFFFFDA) /* PBDR  Address */
+#define MDCR    (*(volatile union  un_mdcr  *)0xFEE011) /* MDCR  Address */
+#define SYSCR   (*(volatile union  un_syscr *)0xFEE012) /* SYSCR Address */
+#define DIVCR   (*(volatile union  un_divcr *)0xFEE01B) /* DIVCR Address */
+#define MSTCR   (*(volatile union  un_mstcr *)0xFEE01C) /* MSTCR Address */
+#define BSC     (*(volatile struct st_bsc   *)0xFEE012) /* BSC   Address */
+#define INTC    (*(volatile struct st_intc  *)0xFEE014) /* INTC  Address */
+#define DMAC0A  (*(volatile struct st_sam   *)0xFFFF20) /* DMAC 0A Addr */
+#define DMAC0B  (*(volatile struct st_sam   *)0xFFFF28) /* DMAC 0B Addr */
+#define DMAC1A  (*(volatile struct st_sam   *)0xFFFF30) /* DMAC 1A Addr */
+#define DMAC1B  (*(volatile struct st_sam   *)0xFFFF38) /* DMAC 1B Addr */
+#define DMAC0   (*(volatile struct st_fam   *)0xFFFF20) /* DMAC 0  Addr */
+#define DMAC1   (*(volatile struct st_fam   *)0xFFFF30) /* DMAC 1  Addr */
+#define FLASH   (*(volatile struct st_flash *)0xFFFF40) /* FLASH Address */
+#define ITU     (*(volatile struct st_itu   *)0xFFFF60) /* ITU   Address */
+#define ITU0    (*(volatile struct st_itu0  *)0xFFFF68) /* ITU0  Address */
+#define ITU1    (*(volatile struct st_itu0  *)0xFFFF70) /* ITU1  Address */
+#define ITU2    (*(volatile struct st_itu0  *)0xFFFF78) /* ITU2  Address */
+#define WDT     (*(volatile union  un_wdt   *)0xFFFF8C) /* WDT   Address */
+#define TMR01   (*(volatile struct st_tmr01 *)0xFFFF80) /* TMR01 Address */
+#define TMR23   (*(volatile struct st_tmr23 *)0xFFFF90) /* TMR23 Address */
+#define TMR0    (*(volatile struct st_tmr0  *)0xFFFF80) /* TMR0  Address */
+#define TMR1    (*(volatile struct st_tmr1  *)0xFFFF81) /* TMR1  Address */
+#define TMR2    (*(volatile struct st_tmr2  *)0xFFFF90) /* TMR2  Address */
+#define TMR3    (*(volatile struct st_tmr1  *)0xFFFF91) /* TMR3  Address */
+#define DASTCR  (*(volatile union  un_dastcr*)0xFEE01A) /* DASTCRAddress */
+#define DA      (*(volatile struct st_da    *)0xFFFF9C) /* D/A   Address */
+#define TPC     (*(volatile struct st_tpc   *)0xFFFFA0) /* TPC   Address */
+#define SCI0    (*(volatile struct st_sci   *)0xFFFFB0) /* SCI0  Address */
+#define SCI1    (*(volatile struct st_sci   *)0xFFFFB8) /* SCI1  Address */
+#define SCI2    (*(volatile struct st_sci   *)0xFFFFC0) /* SCI2  Address */
+#define SMCI0   (*(volatile struct st_smci  *)0xFFFFB0) /* SMCI0 Address */
+#define SMCI1   (*(volatile struct st_smci  *)0xFFFFB8) /* SMCI1 Address */
+#define SMCI2   (*(volatile struct st_smci  *)0xFFFFC0) /* SMCI2 Address */
+#define AD      (*(volatile struct st_ad    *)0xFFFFE0) /* A/D   Address */
+
+#endif                          /* #ifndef __INCLUDE_H83068F_H__ */

include/arch/h8300h/irqreg.h

@@ -0,0 +1,134 @@
+#ifndef _DEV_IRQREG_H8_H_
+#define _DEV_IRQREG_H8_H_
+
+/*
+ * Copyright (C) 2004 by Jan Dubiec. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JAN DUBIEC AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JAN DUBIEC
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $Log: irqreg.h,v $
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ */
+
+enum {
+    IRQ_NMI,
+    IRQ_INT0,
+    IRQ_INT1,
+    IRQ_INT2,
+    IRQ_INT3,
+    IRQ_INT4,
+    IRQ_INT5,
+    IRQ_WOVI,
+    IRQ_CMI,
+    IRQ_ADI,
+    IRQ_IMIA0,
+    IRQ_IMIB0,
+    IRQ_OVI0,
+    IRQ_IMIA1,
+    IRQ_IMIB1,
+    IRQ_OVI1,
+    IRQ_IMIA2,
+    IRQ_IMIB2,
+    IRQ_OVI2,
+    IRQ_CMIA0,
+    IRQ_CMIB0,
+    IRQ_CMIA0_B1,
+    IRQ_TOVI0_1,
+    IRQ_CMIA2,
+    IRQ_CMIB2,
+    IRQ_CMIA2_B3,
+    IRQ_TOVI2_3,
+    IRQ_DEND0A,
+    IRQ_DEND0B,
+    IRQ_DEND1A,
+    IRQ_DEND1B,
+    IRQ_ERI0,
+    IRQ_RXI0,
+    IRQ_TXI0,
+    IRQ_TEI0,
+    IRQ_ERI1,
+    IRQ_RXI1,
+    IRQ_TXI1,
+    IRQ_TEI1,
+    IRQ_ERI2,
+    IRQ_RXI2,
+    IRQ_TXI2,
+    IRQ_TEI2,
+    IRQ_MAX
+};
+
+extern IRQ_HANDLER sig_NMI;
+extern IRQ_HANDLER sig_INT0;
+extern IRQ_HANDLER sig_INT1;
+extern IRQ_HANDLER sig_INT2;
+extern IRQ_HANDLER sig_INT3;
+extern IRQ_HANDLER sig_INT4;
+extern IRQ_HANDLER sig_INT5;
+extern IRQ_HANDLER sig_WOVI;
+extern IRQ_HANDLER sig_CMI;
+extern IRQ_HANDLER sig_ADI;
+extern IRQ_HANDLER sig_IMIA0;
+extern IRQ_HANDLER sig_IMIB0;
+extern IRQ_HANDLER sig_OVI0;
+extern IRQ_HANDLER sig_IMIA1;
+extern IRQ_HANDLER sig_IMIB1;
+extern IRQ_HANDLER sig_OVI1;
+extern IRQ_HANDLER sig_IMIA2;
+extern IRQ_HANDLER sig_IMIB2;
+extern IRQ_HANDLER sig_OVI2;
+extern IRQ_HANDLER sig_CMIA0;
+extern IRQ_HANDLER sig_IMIB0;
+extern IRQ_HANDLER sig_CMIA0_B1;
+extern IRQ_HANDLER sig_TOVI0_1;
+extern IRQ_HANDLER sig_CMIA2;
+extern IRQ_HANDLER sig_IMIB2;
+extern IRQ_HANDLER sig_CMIA2_B3;
+extern IRQ_HANDLER sig_TOVI2_3;
+extern IRQ_HANDLER sig_DEND0A;
+extern IRQ_HANDLER sig_DEND0B;
+extern IRQ_HANDLER sig_DEND1A;
+extern IRQ_HANDLER sig_DEND1B;
+extern IRQ_HANDLER sig_ERI0;
+extern IRQ_HANDLER sig_RXI0;
+extern IRQ_HANDLER sig_TXI0;
+extern IRQ_HANDLER sig_TEI0;
+extern IRQ_HANDLER sig_ERI1;
+extern IRQ_HANDLER sig_RXI1;
+extern IRQ_HANDLER sig_TXI1;
+extern IRQ_HANDLER sig_TEI1;
+extern IRQ_HANDLER sig_ERI2;
+extern IRQ_HANDLER sig_RXI2;
+extern IRQ_HANDLER sig_TXI2;
+extern IRQ_HANDLER sig_TEI2;
+
+#endif

include/arch/m68k.h

@@ -0,0 +1,46 @@
+#ifndef _ARCH_M68K_H_
+#define _ARCH_M68K_H_
+
+/*
+ * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: m68k.h,v $
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ * Revision 1.1  2004/02/01 18:49:48  haraldkipp
+ * Added CPU family support
+ *
+ */
+
+#endif

include/arch/m68k/atom.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: atom.h,v $
+ * Revision 1.2  2005/07/26 15:47:06  haraldkipp
+ * AtomicInc() and AtomicDec() are no longer required by Nut/Net.
+ * Removed to simplify the porting job. Broken applications should
+ * implement their own version.
+ *
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.1  2005/05/27 17:41:52  drsung
+ * Moved the file.
+ *
+ * Revision 1.1  2005/05/26 10:08:42  drsung
+ * Moved the platform dependend code from include/sys/atom.h to this file.
+ *
+ *
+ */
+
+#ifndef _SYS_ATOM_H_
+#error "Do not include this file directly. Use sys/atom.h instead!"
+#endif
+
+/* TODO */
+#define NutEnterCritical()
+/* TODO */
+#define NutExitCritical()
+/* TODO */
+#define NutJumpOutCritical()

include/arch/m68k/irqreg.h

@@ -0,0 +1,124 @@
+#ifndef _DEV_IRQREG_M68K_H_
+#define _DEV_IRQREG_M68K_H_
+
+/*
+ * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: irqreg.h,v $
+ * Revision 1.1  2005/07/26 18:35:09  haraldkipp
+ * First check in
+ *
+ * Revision 1.1  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ *
+ */
+
+enum {
+    IRQ_INT0,
+    IRQ_INT1,
+    IRQ_INT2,
+    IRQ_INT3,
+    IRQ_INT4,
+    IRQ_INT5,
+    IRQ_INT6,
+    IRQ_INT7,
+    IRQ_TIMER2_COMP,
+    IRQ_TIMER2_OVF,
+    IRQ_TIMER1_CAPT,
+    IRQ_TIMER1_COMPA,
+    IRQ_TIMER1_COMPB,
+    IRQ_TIMER1_OVF,
+    IRQ_TIMER0_COMP,
+    IRQ_TIMER0_OVF,
+    IRQ_SPI_STC,
+    IRQ_UART_RX,
+    IRQ_UART_UDRE,
+    IRQ_UART_TX,
+    IRQ_ADC,
+    IRQ_EE_RDY,
+    IRQ_ANA_COMP,
+#ifdef __AVR_ATmega128__
+    IRQ_TIMER1_COMPC,
+    IRQ_TIMER3_CAP,
+    IRQ_TIMER3_COMPA,
+    IRQ_TIMER3_COMPB,
+    IRQ_TIMER3_COMPC,
+    IRQ_TIMER3_OVF,
+    IRQ_UART1_RX,
+    IRQ_UART1_UDRE,
+    IRQ_UART1_TX,
+    IRQ_I2C,
+    IRQ_SPM_RDY,
+#endif
+    IRQ_MAX
+};
+
+extern IRQ_HANDLER sig_INTERRUPT0;
+extern IRQ_HANDLER sig_INTERRUPT1;
+extern IRQ_HANDLER sig_INTERRUPT2;
+extern IRQ_HANDLER sig_INTERRUPT3;
+extern IRQ_HANDLER sig_INTERRUPT4;
+extern IRQ_HANDLER sig_INTERRUPT5;
+extern IRQ_HANDLER sig_INTERRUPT6;
+extern IRQ_HANDLER sig_INTERRUPT7;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE2;
+extern IRQ_HANDLER sig_OVERFLOW2;
+extern IRQ_HANDLER sig_INPUT_CAPTURE1;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1B;
+extern IRQ_HANDLER sig_OVERFLOW1;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE0;
+extern IRQ_HANDLER sig_OVERFLOW0;
+extern IRQ_HANDLER sig_SPI;
+extern IRQ_HANDLER sig_UART0_TRANS;
+extern IRQ_HANDLER sig_UART0_DATA;
+extern IRQ_HANDLER sig_UART0_RECV;
+extern IRQ_HANDLER sig_ADC;
+extern IRQ_HANDLER sig_EEPROM_READY;
+extern IRQ_HANDLER sig_COMPARATOR;
+#ifdef __AVR_ATmega128__
+extern IRQ_HANDLER sig_OUTPUT_COMPARE1C;
+extern IRQ_HANDLER sig_INPUT_CAPTURE3;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3A;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3B;
+extern IRQ_HANDLER sig_OUTPUT_COMPARE3C;
+extern IRQ_HANDLER sig_OVERFLOW3;
+extern IRQ_HANDLER sig_UART1_RECV;
+extern IRQ_HANDLER sig_UART1_DATA;
+extern IRQ_HANDLER sig_UART1_TRANS;
+extern IRQ_HANDLER sig_2WIRE_SERIAL;
+extern IRQ_HANDLER sig_SPM_READY;
+#endif
+
+#endif

include/arch/timer.h

@@ -0,0 +1,78 @@
+#ifndef _ARCH_TIMER_H_
+#define _ARCH_TIMER_H_
+
+/*
+ * <MFS> Modified for Streamit
+ * Added timer modifications from Harald Kipp, 2008/07/29 + new NutDelay implementation
+ *
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: timer.h,v $
+ * Revision 1.2  2008/07/08 08:25:05  haraldkipp
+ * NutDelay is no more architecture specific.
+ * Number of loops per millisecond is configurable or will be automatically
+ * determined.
+ * A new function NutMicroDelay provides shorter delays.
+ *
+ * Revision 1.1  2005/07/26 18:42:19  haraldkipp
+ * First check in
+ *
+ */
+
+#if defined(__AVR__)
+#include <arch/avr/timer.h>
+#elif defined(__arm__)
+#include <arch/arm/timer.h>
+#elif defined(__H8300H__) || defined(__H8300S__)
+#include <arch/h8300h/timer.h>
+#elif defined(__m68k__)
+#include <arch/m68k/timer.h>
+#elif defined(__linux__) || defined(__APPLE__) || defined(__CYGWIN__)
+#include <arch/unix/timer.h>
+#endif
+
+__BEGIN_DECLS
+/* Prototypes */
+
+/*
+ * Architecture dependent functions.
+ */
+extern void NutRegisterTimer(void (*handler) (void *));
+extern u_long NutGetCpuClock(void);
+extern u_long NutGetTickClock(void);
+extern u_long NutTimerMillisToTicks(u_long ms);
+
+__END_DECLS
+/* End of prototypes */
+
+#endif

include/arch/unix.h

@@ -0,0 +1,159 @@
+#ifndef _ARCH_UNIX_H_
+#define _ARCH_UNIX_H_
+
+/*
+ * Copyright (C) 2000-2004 by ETH Zurich
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ETH ZURICH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ETH ZURICH
+ *  OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * unix.h.c - types and defines for unix emulation
+ *
+ * 2004.04.01 Matthias Ringwald <matthias.ringwald@inf.ethz.ch>
+ *
+ */
+
+
+#if !defined(__linux__) && !defined(__APPLE__) && !defined(__CYGWIN__)
+#error "Nut/OS emulation currently runs only on Linux and MAC OS X systems."
+#endif
+
+/* -------------------------------------------------------------------------
+ * map some AVR types/defines to something else
+ * ------------------------------------------------------------------------- */
+
+#define CONST      const
+#define INLINE     inline
+
+#define PSTR(p)    (p)
+#define PRG_RDB(p) (*((const char *)(p)))
+
+#define prog_char  const char
+#define PGM_P      prog_char *
+
+/* -------------------------------------------------------------------------
+ * now we can include types (and time.h)
+ * ------------------------------------------------------------------------- */
+
+#include <sys/types.h>
+#include <dev/mweeprom.h>
+#include <termios.h>
+#include <unistd_orig.h>
+
+
+/* -------------------------------------------------------------------------
+ * redefine main
+ * ------------------------------------------------------------------------- */
+
+#define main(...)       NutAppMain(__VA_ARGS__)
+
+/* -------------------------------------------------------------------------
+ * map harvard specific calls to normal ones
+ * ------------------------------------------------------------------------- */
+
+
+#define strlen_P(x)             strlen(x)
+#define strcpy_P(x,y)           strcpy(x,y)
+#define strcmp_P(x, y)          strcmp(x, y)
+#define memcpy_P(x, y, z)       memcpy(x, y, z)
+
+/* -------------------------------------------------------------------------
+ * emulated IRQs
+ * ------------------------------------------------------------------------- */
+enum {
+	IRQ_TIMER0,
+    IRQ_UART0_RX,
+    IRQ_UART1_RX,
+    IRQ_UART2_RX,
+	IRQ_MAX
+};
+
+/* -------------------------------------------------------------------------
+ * emulated heap
+ * ------------------------------------------------------------------------- */
+
+/* RAMSTART could be zero, but RAMSTART < 3 leads to a crash in freopen (stdout) */
+#define RAMSTART    ((void *)0x00100)
+
+/* on linux our malloc function makes the init section crash, so we better rename it */
+#define malloc(...)		NUT_malloc(__VA_ARGS__)
+#define free(...)		NUT_free(__VA_ARGS__)
+
+/* -------------------------------------------------------------------------
+ * parsing of command line options
+ * ------------------------------------------------------------------------- */
+
+/*
+ * options of one uart 
+ * usbnum: a negative usbnum is used to indicate that device name is used
+ */
+
+typedef struct {
+
+    char *device;
+    u_long bautrate;
+    u_char flowcontrol;
+    signed char usbnum;
+} uart_options_t;
+
+/* 
+ * all command line options
+ */
+typedef struct {
+
+    // debug output
+    int verbose;
+
+    uart_options_t uart_options[3];
+    struct termios saved_termios;
+} emulation_options_t;
+
+/* the command line options are stored here */
+extern emulation_options_t emulation_options;
+
+/* -------------------------------------------------------------------------
+ * function declarations
+ * ------------------------------------------------------------------------- */
+void emulation_options_parse(int argc, char *argv[]);
+
+/** \name Backwards compatibility defines */
+#define eeprom_rb(addr) eeprom_read_byte       ((u_char  *)(u_long) (addr))
+#define eeprom_rw(addr) eeprom_read_word       ((u_short *)(u_long) (addr))
+#define eeprom_wb(addr, val) eeprom_write_byte ((u_char  *)(u_long) (addr), (val))
+// fake ATmega128 has 0xfff eeprom
+#define    E2END    0x0FFF
+
+/** \def eeprom_is_ready
+    \ingroup unix_eeprom
+    always returns 1, as eeprom = unix_file is always ready */
+#define eeprom_is_ready() TRUE
+
+#endif                          /* #ifndef _CPU_UNIX_H_ */

include/arch/unix/atom.h

@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: atom.h,v $
+ * Revision 1.2  2006/01/26 15:34:49  going_nuts
+ * adapted to new interrupt handling scheme for unix emulation
+ * now uses Unix timer and runs without interrupts unless you emulate other hardware
+ *
+ * Revision 1.1  2005/06/06 10:49:35  haraldkipp
+ * Building outside the source tree failed. All header files moved from
+ * arch/cpu/include to include/arch/cpu.
+ *
+ * Revision 1.1  2005/05/27 17:41:52  drsung
+ * Moved the file.
+ *
+ * Revision 1.1  2005/05/26 10:08:42  drsung
+ * Moved the platform dependend code from include/sys/atom.h to this file.
+ *
+ *
+ */
+
+#ifndef _SYS_ATOM_H_
+#error "Do not include this file directly. Use sys/atom.h instead!"
+#endif
+
+__BEGIN_DECLS
+#include <pthread.h>
+#include <signal.h>
+#include <sys/thread.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+extern u_short main_cs_level;
+extern sigset_t irq_signal;
+extern pthread_cond_t irq_cv;
+extern u_short int_disabled;
+
+extern FILE *__os_trs;
+extern u_char __os_trf;
+
+#define AtomicInc(p)     (++(*p))
+#define AtomicDec(p)     (--(*p))
+
+extern void NutExitCritical(void);
+extern void NutEnterCritical(void);
+
+
+// uncommenting the following causes a segmentation fault because stdout isn't defined at startup.
+// #define CRITSECT_TRACE
+
+#ifndef CRITSECT_TRACE
+#define NutEnterCritical()                                                  \
+    pthread_sigmask(SIG_BLOCK, &irq_signal, 0);         \
+    int_disabled = 1;                                   \
+    if (runningThread) {                                \
+        runningThread->td_cs_level++;                   \
+    } else {                                            \
+        main_cs_level++;                                \
+    }                                                   \
+    pthread_sigmask(SIG_UNBLOCK, &irq_signal, 0);
+
+
+#define NutExitCritical()                                                           \
+    pthread_sigmask(SIG_BLOCK, &irq_signal, 0);         \
+    if (runningThread) {                                \
+        if (--runningThread->td_cs_level == 0) {        \
+            int_disabled = 0;                           \
+            pthread_cond_signal(&irq_cv);               \
+        }                                               \
+    } else {                                            \
+        if (--main_cs_level == 0) {                     \
+            int_disabled = 0;                           \
+            pthread_cond_signal(&irq_cv);               \
+        }                                               \
+    }                                                   \
+    pthread_sigmask(SIG_UNBLOCK, &irq_signal, 0);
+
+#else
+
+#define NutEnterCritical()                                           \
+    pthread_sigmask(SIG_BLOCK, &irq_signal, 0);         \
+    int_disabled = 1;                                   \
+    if (runningThread) {                                \
+        if (runningThread->td_cs_level==0)                                              \
+            printf("Entered a: %s.%d - %s\n", __FILE__, __LINE__, runningThread->td_name);  \
+        runningThread->td_cs_level++;                   \
+    } else {                                            \
+        if (main_cs_level==0)                                               \
+            printf("Entered b: %s.%d - %s\n", __FILE__, __LINE__, "ROOT");  \
+        main_cs_level++;                                \
+    }                                                   \
+    pthread_sigmask(SIG_UNBLOCK, &irq_signal, 0);
+
+#define NutExitCritical()                                                                       \
+    pthread_sigmask(SIG_BLOCK, &irq_signal, 0);         \
+    if (runningThread) {                                \
+        if (--runningThread->td_cs_level == 0) {        \
+            int_disabled = 0;                           \
+            printf("Left a: %s.%d - %s\n", __FILE__, __LINE__, runningThread->td_name); \
+            pthread_cond_signal(&irq_cv);               \
+        }                                               \
+    } else {                                            \
+        if (--main_cs_level == 0) {                     \
+            int_disabled = 0;                           \
+            printf("Left a: %s.%d - %s\n", __FILE__, __LINE__, "ROOT"); \
+            pthread_cond_signal(&irq_cv);               \
+        }                                               \
+    }                                                   \
+    pthread_sigmask(SIG_UNBLOCK, &irq_signal, 0);
+#endif
+
+#define NutJumpOutCritical() NutExitCritical()
+
+__END_DECLS

include/arch/unix/irqreg.h

@@ -0,0 +1,64 @@
+#ifndef _DEV_IRQREG_UNIX_H_
+#define _DEV_IRQREG_UNIX_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: irqreg.h,v $
+ * Revision 1.2  2006/01/26 15:34:49  going_nuts
+ * adapted to new interrupt handling scheme for unix emulation
+ * now uses Unix timer and runs without interrupts unless you emulate other hardware
+ *
+ * Revision 1.1  2005/07/26 18:35:10  haraldkipp
+ * First check in
+ *
+ * Revision 1.1  2005/04/07 12:31:37  freckle
+ * most unix emulation specific stuff now in irqreg_unix.h.
+ * corrected #warning "MCU not defined"
+ *
+ */
+
+#include <signal.h>
+
+__BEGIN_DECLS
+
+extern u_char irq_processed;
+extern pthread_cond_t irq_cv;
+extern sigset_t irq_signal;
+
+extern void NutUnixIrqEventPostAsync(u_char irq_nr, HANDLE * queue );
+extern void NutUnixRaiseInterrupt(int irq);
+
+__END_DECLS
+
+#endif

include/arch/unix/timer.h

@@ -0,0 +1,62 @@
+#ifndef _ARCH_UNIX_TIMER_H_
+#define _ARCH_UNIX_TIMER_H_
+
+/*
+ * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: timer.h,v $
+ * Revision 1.2  2006/01/26 15:34:49  going_nuts
+ * adapted to new interrupt handling scheme for unix emulation
+ * now uses Unix timer and runs without interrupts unless you emulate other hardware
+ *
+ * Revision 1.1  2005/07/26 18:35:10  haraldkipp
+ * First check in
+ *
+ */
+
+/*
+ * This will need work to individually enable/disable single interrupts
+ * For now, this feature is not supported.
+ */
+#define NutEnableTimerIrq()    
+#define NutDisableTimerIrq()    
+
+/*
+ * Previously, the following two setting were used:
+ * #define NutEnableTimerIrq()     NutEnterCritical()
+ * #define NutDisableTimerIrq()    NutExitCritical()
+ * That doesn't work as our NutEnterCritical() disables all interrupts.
+ * Anyway, I think it should have been reversed anyway.
+ */
+#endif
+

include/arpa/inet.h

@@ -0,0 +1,73 @@
+#ifndef _ARPA_INET_H_
+#define _ARPA_INET_H_
+
+/*
+ * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: inet.h,v $
+ * Revision 1.2  2006/03/16 15:25:29  haraldkipp
+ * Changed human readable strings from u_char to char to stop GCC 4 from
+ * nagging about signedness.
+ *
+ * Revision 1.1.1.1  2003/05/09 14:41:03  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.7  2003/05/06 18:38:50  harald
+ * Cleanup
+ *
+ * Revision 1.6  2003/02/04 18:00:36  harald
+ * Version 3 released
+ *
+ * Revision 1.5  2002/08/08 17:22:47  harald
+ * *** empty log message ***
+ *
+ * Revision 1.4  2002/06/26 17:29:14  harald
+ * First pre-release with 2.4 stack
+ *
+ */
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+/*!
+ * \file arpa/inet.h
+ * \brief Internet address conversion.
+ */
+extern u_long inet_addr(CONST char *str);
+extern char *inet_ntoa(u_long addr);
+
+__END_DECLS
+
+#endif

include/cfg/ahdlc.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_AHDLC_H_
+#define _CFG_AHDLC_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/ahdlc.h
+ * \brief AHDLC driver configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: ahdlc.h,v $
+ * Revision 1.1  2005/04/05 17:46:24  haraldkipp
+ * Initial check in.
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/arch.h

@@ -0,0 +1,109 @@
+#ifndef _CFG_ARCH_H_
+#define _CFG_ARCH_H_
+
+/*
+ * Copyright (C) 2004-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: arch.h,v $
+ * Revision 1.3  2007/04/12 09:21:10  haraldkipp
+ * Added ATmega2561 definitions for Ethernut 1 and 2.
+ *
+ * Revision 1.2  2006/05/25 09:22:47  haraldkipp
+ * The PLATFORM definition broke source tree building.
+ * Fixed for Ethernut Boards.
+ *
+ * Revision 1.1  2004/09/19 12:31:52  haraldkipp
+ * Configuration placeholders added
+ *
+ */
+
+/*
+ * This file is reserved to specify architecture dependant
+ * configuration and is currently used as a placeholder 
+ * when not using the Configurator.
+ */
+
+#if defined(ETHERNUT1)
+
+#ifndef PLATFORM
+#define PLATFORM ETHERNUT1
+#endif
+
+#ifndef AVR_GCC
+#define AVR_GCC
+#endif
+
+#if !defined(MCU_ATMEGA128) && !defined(MCU_ATMEGA2561)
+#if defined(__AVR_ATmega2561__) || defined(ATMega2561)
+#define MCU_ATMEGA2561
+#else
+#define MCU_ATMEGA128
+#endif
+#endif
+
+#elif defined(ETHERNUT2)
+
+#ifndef PLATFORM
+#define PLATFORM ETHERNUT2
+#endif
+
+#ifndef AVR_GCC
+#define AVR_GCC
+#endif
+
+#if !defined(MCU_ATMEGA128) && !defined(MCU_ATMEGA2561)
+#if defined(__AVR_ATmega2561__) || defined(ATMega2561)
+#define MCU_ATMEGA2561
+#else
+#define MCU_ATMEGA128
+#endif
+#endif
+
+#elif defined(ETHERNUT3)
+
+#ifndef PLATFORM
+#define PLATFORM ETHERNUT3
+#endif
+
+#ifndef ARM_GCC
+#define ARM_GCC
+#endif
+
+#ifndef MCU_AT91R40008
+#define MCU_AT91R40008
+#endif
+
+#endif /* ETHERNUT3 */
+
+#endif

include/cfg/arch/armpio.h

@@ -0,0 +1,58 @@
+#ifndef _CFG_ARCH_ARMPIO_H_
+#define _CFG_ARCH_ARMPIO_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: armpio.h,v $
+ * Revision 1.1  2006/04/07 15:31:19  haraldkipp
+ * First check in
+ *
+ */
+
+/*!
+ * \file cfg/arch/armpio.h
+ * \brief ARM port configuration.
+ *
+ * This file collects all port specifications for the ARM platform and 
+ * provides an overview of hardware resources in use.
+ *
+ * Values are geared to the Ethernut reference design and can be changed 
+ * by the Configurator. This program creates a file with the same name
+ * in the build tree, which replaces this placeholder.
+ */
+
+
+#endif
+

include/cfg/arch/avr.h

@@ -0,0 +1,85 @@
+#ifndef _CFG_ARCH_AVR_H_
+#define _CFG_ARCH_AVR_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: avr.h,v $
+ * Revision 1.6  2007/04/12 09:10:29  haraldkipp
+ * PORTH added.
+ *
+ * Revision 1.5  2005/08/02 17:46:48  haraldkipp
+ * Major API documentation update.
+ *
+ * Revision 1.4  2005/02/02 20:03:46  haraldkipp
+ * All definitions had been moved to avrpio.h in order to fix the broken
+ * port I/O without being forced to change other existing modules.
+ *
+ * Revision 1.3  2005/01/22 19:27:19  haraldkipp
+ * Changed AVR port configuration names from PORTx to AVRPORTx.
+ *
+ * Revision 1.2  2004/09/22 08:18:57  haraldkipp
+ * More configurable ports
+ *
+ * Revision 1.1  2004/08/25 10:58:02  haraldkipp
+ * New include directory cfg/arch added, which is used for target specific items,
+ * mainly port usage or MCU specific register settings.
+ *
+ */
+
+/*!
+ * \addtogroup xgConfigAvr
+ */
+/*@{*/
+
+/*!
+ * \file include/cfg/arch/avr.h
+ * \brief AVR hardware configuration.
+ */
+
+
+#define AVRPORTA    1
+#define AVRPORTB    2
+#define AVRPORTC    3
+#define AVRPORTD    4
+#define AVRPORTE    5
+#define AVRPORTF    6
+#define AVRPORTG    7
+#define AVRPORTH    8
+
+#include <cfg/arch/avrpio.h>
+
+/*@}*/
+
+#endif

include/cfg/arch/avrpio.h

@@ -0,0 +1,187 @@
+#ifndef _CFG_ARCH_AVRPIO_H_
+#define _CFG_ARCH_AVRPIO_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: avrpio.h,v $
+ * Revision 1.3  2005/07/26 16:06:20  haraldkipp
+ * Added missing SPIDIGIO registers.
+ *
+ * Revision 1.2  2005/02/02 20:06:37  haraldkipp
+ * This file will now contain the AVR port definitions, which were
+ * previously specified in avr.h. This file will be included by avr.h,
+ * so existing code should continue to run without change.
+ *
+ * Revision 1.1  2004/08/25 10:58:02  haraldkipp
+ * New include directory cfg/arch added, which is used for target specific items,
+ * mainly port usage or MCU specific register settings.
+ *
+ */
+
+/*!
+ * \file cfg/arch/avrpio.h
+ * \brief AVR port configuration.
+ *
+ * This file collects all port specifications for the AVR platform and 
+ * provides an overview of hardware resources in use.
+ *
+ * Values are geared to the Ethernut reference design and can be changed 
+ * by the Configurator. This program creates a file with the same name
+ * in the build tree, which replaces this placeholder.
+ */
+
+/*!
+ * \brief USART settings.
+ */
+//#define UART0_RTS_BIT 2
+//#define UART0_CTS_IRQ INT7
+
+#ifdef UART0_RTS_BIT
+#ifndef UART0_RTS_AVRPORT
+#define UART0_RTS_AVRPORT AVRPORTE
+#endif
+#endif /* UART0_RTS_BIT */
+
+
+//#define UART1_RTS_BIT 2
+//#define UART1_CTS_IRQ INT7
+
+#ifdef UART1_RTS_BIT
+#ifndef UART1_RTS_AVRPORT
+#define UART1_RTS_AVRPORT AVRPORTE
+#endif
+#endif /* UART1_RTS_BIT */
+
+/*!
+ * \brief Settings for the Realtek RTL8019AS.
+ */
+
+#ifndef RTL_BASE_ADDR
+/*!
+ * \brief Memory mapped base address.
+ */
+#define RTL_BASE_ADDR 0x8300
+#endif
+
+#ifndef RTL_SIGNAL_IRQ
+/*!
+ * \brief Interrupt used by the controller.
+ */
+#define RTL_SIGNAL_IRQ INT5
+#endif
+
+#ifndef RTL_EESK_BIT
+/*!
+ * \brief Clock input for EEPROM emulation.
+ *
+ * This is enabled by default, but the driver will run a check before
+ * jumping into the emulation.
+ */
+#define RTL_EESK_BIT 5
+#endif
+
+#ifndef RTL_EESK_AVRPORT
+#define RTL_EESK_AVRPORT AVRPORTC
+#endif
+
+#ifndef RTL_EEDO_BIT
+#define RTL_EEDO_BIT 6
+#endif
+
+#ifndef RTL_EEDO_AVRPORT
+#define RTL_EEDO_AVRPORT AVRPORTC
+#endif
+
+#ifndef RTL_EEMU_BIT
+#define RTL_EEMU_BIT 7
+#endif
+
+#ifndef RTL_EEMU_AVRPORT
+#define RTL_EEMU_AVRPORT AVRPORTC
+#endif
+
+/*!
+ * \brief Port usage of digital I/O shift register.
+ */
+#ifndef SPIDIGIO_SOUT_BIT
+#define SPIDIGIO_SOUT_BIT 5
+#endif
+
+#ifndef SPIDIGIO_SOUT_AVRPORT
+#define SPIDIGIO_SOUT_AVRPORT AVRPORTD
+#endif
+
+#ifndef SPIDIGIO_SIN_BIT
+#define SPIDIGIO_SIN_BIT 6
+#endif
+
+#ifndef SPIDIGIO_SIN_PIN
+#define SPIDIGIO_SIN_PIN PIND
+#endif
+
+#ifndef SPIDIGIO_SIN_PORT
+#define SPIDIGIO_SIN_PORT PORTD
+#endif
+
+#ifndef SPIDIGIO_SIN_DDR
+#define SPIDIGIO_SIN_DDR DDRD
+#endif
+
+#ifndef SPIDIGIO_SCLK_BIT
+#define SPIDIGIO_SCLK_BIT 7
+#endif
+
+#ifndef SPIDIGIO_SCLK_AVRPORT
+#define SPIDIGIO_SCLK_AVRPORT AVRPORTD
+#endif
+
+#ifndef SPIDIGIO_LDI_BIT
+#define SPIDIGIO_LDI_BIT 7
+#endif
+
+#ifndef SPIDIGIO_LDI_AVRPORT
+#define SPIDIGIO_LDI_AVRPORT AVRPORTB
+#endif
+
+#ifndef SPIDIGIO_LDO_BIT
+#define SPIDIGIO_LDO_BIT 5
+#endif
+
+#ifndef SPIDIGIO_LDO_AVRPORT
+#define SPIDIGIO_LDO_AVRPORT AVRPORTB
+#endif
+
+#endif
+

include/cfg/arch/gpio.h

@@ -0,0 +1,56 @@
+#ifndef _CFG_ARCH_GPIO_H_
+#define _CFG_ARCH_GPIO_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: gpio.h,v $
+ * Revision 1.1  2006/04/07 15:31:19  haraldkipp
+ * First check in
+ *
+ */
+
+/*!
+ * \file cfg/arch/gpio.h
+ * \brief Port configuration.
+ */
+
+#if defined(__AVR__)
+#include <cfg/arch/avr.h>
+#elif defined(__arm__)
+#include <cfg/arch/armpio.h>
+#endif
+
+#endif
+

include/cfg/arp.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_ARP_H_
+#define _CFG_ARP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/arp.h
+ * \brief ARP configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: arp.h,v $
+ * Revision 1.1  2005/02/04 14:26:20  haraldkipp
+ * First check in
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/audio.h

@@ -0,0 +1,48 @@
+#ifndef _CFG_AUDIO_H_
+#define _CFG_AUDIO_H_
+
+/*
+ * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: audio.h,v $
+ * Revision 1.1  2007/04/12 08:59:55  haraldkipp
+ * VS10XX decoder support added.
+ *
+ */
+
+/*
+ * This file is reserved for platform independent audio driver configurations.
+ */
+
+#endif

include/cfg/bankmem.h

@@ -0,0 +1,61 @@
+#ifndef _CFG_BANKMEM_H_
+#define _CFG_BANKMEM_H_
+
+/*
+ * Copyright (C) 2003-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: bankmem.h,v $
+ * Revision 1.3  2004/08/25 10:56:10  haraldkipp
+ * More general memory layout definitions moved from cfg/bankmem.h to cfg/memory.h.
+ *
+ * Revision 1.2  2004/08/18 22:34:08  drsung
+ * Final #endif was missing.
+ *
+ * Revision 1.1  2004/08/18 18:51:41  haraldkipp
+ * Made banked memory configurable.
+ *
+ */
+
+/*!
+ * \file cfg/bankmem.h
+ * \brief Banked memory default configuration.
+ *
+ * Values can be changed by the configurator.
+ *
+ * \todo Add configuration items instead of occupying all banks.
+ */
+
+#include <cfg/memory.h>
+
+#endif /* #ifndef _CFG_BANKMEM_H_ */

include/cfg/chat.h

@@ -0,0 +1,53 @@
+#ifndef _CFG_CHAT_H_
+#define _CFG_CHAT_H_
+
+/*
+ * Copyright (C) 2003-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: chat.h,v $
+ * Revision 1.1  2004/11/24 15:27:20  haraldkipp
+ * Made options cnfigurable
+ *
+ */
+
+/*!
+ * \file cfg/chat.h
+ * \brief UART chat default configuration.
+ *
+ * This file serves as a placeholder. 
+ * Values can be changed by the configurator.
+ *
+ */
+
+#endif /* #ifndef _CFG_CHAT_H_ */

include/cfg/clock.h

@@ -0,0 +1,83 @@
+#ifndef _CFG_CLOCK_H_
+#define _CFG_CLOCK_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/clock.h
+ * \brief Nut/OS Clock Configuration.
+ *
+ * This file is reserved for kernel related configurations when building 
+ * the system in the source tree without using the Configurator.
+ *
+ * When creating a new build tree with the Configurator, then it will
+ * be replaced by a file with the same name, which is located in the
+ * build tree.
+ *
+ * \verbatim
+ *
+ * $Log: clock.h,v $
+ * Revision 1.1  2006/01/05 16:32:00  haraldkipp
+ * First check-in.
+ *
+ *
+ * \endverbatim
+ */
+
+/* Default configuration for Ethernut 3. */
+#if 0
+
+/*! \brief PLL Clock Output that is used for the CPU Clock. */
+#ifndef NUT_PLL_CPUCLK
+#define NUT_PLL_CPUCLK 3
+#endif
+
+/*! \brief PLL Clock Output that is used for the Ethernet Controller Clock. */
+#ifndef NUT_PLL_ETHCLK
+#define NUT_PLL_ETHCLK 1
+#endif
+
+/*! \brief PLL Clock Output that is fed to the GCK1 Pin of the CPLD. */
+#ifndef NUT_PLL_NPLCLK1
+#define NUT_PLL_NPLCLK1 2
+#endif
+
+/*! \brief PLL Clock Output that is fed to the GCK3 Pin of the CPLD. */
+#ifndef NUT_PLL_NPLCLK3
+#define NUT_PLL_NPLCLK3 4
+#endif
+
+#endif /* Ethernut 3 */
+
+#endif

include/cfg/coconut.h

@@ -0,0 +1,183 @@
+#ifndef _CFG_COCONUT_H_
+#define _CFG_COCONUT_H_
+
+/*
+ * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: coconut.h,v $
+ * Revision 1.4  2005/01/22 19:26:33  haraldkipp
+ * Marked deprecated.
+ *
+ * Revision 1.3  2003/08/05 20:17:46  haraldkipp
+ * Typing errors corrected
+ *
+ * Revision 1.2  2003/05/15 15:47:30  haraldkipp
+ * Conflict with NIC interrupt and LEDL removed.
+ *
+ * Revision 1.1.1.1  2003/05/09 14:41:04  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.2  2003/05/06 18:39:12  harald
+ * Cleanup
+ *
+ */
+
+/*!
+ * \file cfg/coconut.h
+ * \brief Coconut hardware specification.
+ *
+ * Including this file is deprecated. Use cfg/arch/avr.h.
+ */
+/*
+ * \addtogroup xgCoconutCfg
+ */
+/*@{*/
+
+/*
+ * Coconut LEDs.
+ */
+#define COCO_LED0_PORT  PORTB
+#define COCO_LED0_DDR   DDRB
+#define COCO_LED0_BIT   4
+
+#define COCO_LED1_PORT  PORTB
+#define COCO_LED1_DDR   DDRB
+#define COCO_LED1_BIT   6
+
+/*
+ * Coconut handshake lines.
+ */
+#define COCO_HSO0_PORT  PORTE
+#define COCO_HSO0_DDR   DDRE
+#define COCO_HSO0_BIT   2
+
+#define COCO_HSI0_PORT  PORTE
+#define COCO_HSI0_DDR   DDRE
+#define COCO_HSI0_BIT   6
+
+#define COCO_HSO1_PORT  PORTD
+#define COCO_HSO1_DDR   DDRD
+#define COCO_HSO1_BIT   4
+
+#define COCO_HSI1_PORT  PORTE
+#define COCO_HSI1_DDR   DDRE
+#define COCO_HSI1_BIT   7
+
+#define COCO_HS0_SIGNAL sig_INTERRUPT6
+#define COCO_HS1_SIGNAL sig_INTERRUPT7
+
+/*
+ * Ethernut reset lines.
+ */
+#define ENUT_RST0_PORT  PORTB
+#define ENUT_RST0_DDR   DDRB
+#define ENUT_RST0_BIT   0
+
+#define ENUT_RST1_PORT  PORTB
+#define ENUT_RST1_DDR   DDRB
+#define ENUT_RST1_BIT   1
+
+#define ENUT_RST2_PORT  PORTB
+#define ENUT_RST2_DDR   DDRB
+#define ENUT_RST2_BIT   2
+
+/*
+ * Ethernut LEDs.
+ * LEDA (activity) with 1k resistor to ground.
+ * LEDL (link) moved from PE5 to PE4. PE5 is NIC IRQ.
+ */
+#define ENUT_LED0_PORT  PORTB
+#define ENUT_LED0_DDR   DDRB
+#define ENUT_LED0_BIT   4
+
+#define ENUT_LED1_PORT  PORTB
+#define ENUT_LED1_DDR   DDRB
+#define ENUT_LED1_BIT   6
+
+#define ENUT_LEDL_PORT  PORTE
+#define ENUT_LEDL_DDR   DDRE
+#define ENUT_LEDL_BIT   4
+
+#define ENUT_LEDA_PORT  PORTE
+#define ENUT_LEDA_DDR   DDRE
+#define ENUT_LEDA_BIT   6
+
+/*
+ * Ethernut SPI I/O.
+ */
+#define ENUT_SOUT_PORT  PORTD
+#define ENUT_SOUT_DDR   DDRD
+#define ENUT_SOUT_BIT   6
+
+#define ENUT_SIN_PORT   PORTD
+#define ENUT_SIN_DDR    DDRD
+#define ENUT_SIN_BIT    7
+
+#define ENUT_SCLK_PORT  PORTD
+#define ENUT_SCLK_DDR   DDRD
+#define ENUT_SCLK_BIT   5
+
+#define ENUT_LDI_PORT   PORTB
+#define ENUT_LDI_DDR    DDRB
+#define ENUT_LDI_BIT    7
+
+#define ENUT_LDO_PORT   PORTB
+#define ENUT_LDO_DDR    DDRB
+#define ENUT_LDO_BIT    5
+
+/*
+ * Ethernut handshake lines.
+ * No interrupt on HSI0.
+ */
+#define ENUT_HSO0_PORT  PORTE
+#define ENUT_HSO0_DDR   DDRE
+#define ENUT_HSO0_BIT   2
+
+#define ENUT_HSI0_PORT  PORTE
+#define ENUT_HSI0_DDR   DDRE
+#define ENUT_HSI0_BIT   3
+
+#define ENUT_HSO1_PORT  PORTD
+#define ENUT_HSO1_DDR   DDRD
+#define ENUT_HSO1_BIT   4
+
+#define ENUT_HSI1_PORT  PORTE
+#define ENUT_HSI1_DDR   DDRE
+#define ENUT_HSI1_BIT   7
+
+#define ENUT_HS1_SIGNAL sig_INTERRUPT7
+
+/*@}*/
+
+#endif

include/cfg/crt.h

@@ -0,0 +1,49 @@
+#ifndef _CFG_CRT_H_
+#define _CFG_CRT_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: crt.h,v $
+ * Revision 1.1  2004/09/19 12:31:52  haraldkipp
+ * Configuration placeholders added
+ *
+ */
+
+/*
+ * This file is reserved for C runtime related configurations
+ * like wether floating point is used or not.
+ */
+
+#endif

include/cfg/dev.h

@@ -0,0 +1,53 @@
+#ifndef _CFG_DEV_H_
+#define _CFG_DEV_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: dev.h,v $
+ * Revision 1.2  2006/02/23 15:46:15  haraldkipp
+ * Including this one may have exclude cfg/os.h.
+ *
+ * Revision 1.1  2004/09/22 08:18:58  haraldkipp
+ * More configurable ports
+ *
+ */
+
+/*
+ * This file is reserved for platform independent device configurations.
+ *
+ */
+
+#endif
+

include/cfg/dhcp.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_DHCP_H_
+#define _CFG_DHCP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/dhcp.h
+ * \brief DHCP configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: dhcp.h,v $
+ * Revision 1.1  2005/02/04 14:26:20  haraldkipp
+ * First check in
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/eeprom.h

@@ -0,0 +1,50 @@
+#ifndef _CFG_EEPROM_H_
+#define _CFG_EEPROM_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: eeprom.h,v $
+ * Revision 1.1  2004/09/19 12:31:52  haraldkipp
+ * Configuration placeholders added
+ *
+ */
+
+/*
+ * This file is reserved for EEPROM related configurations.
+ *
+ */
+
+#endif
+

include/cfg/ethernut.h

@@ -0,0 +1,121 @@
+#ifndef _CFG_ETHERNUT_H_
+#define _CFG_ETHERNUT_H_
+
+/*
+ * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: ethernut.h,v $
+ * Revision 1.3  2005/01/22 19:26:33  haraldkipp
+ * Marked deprecated.
+ *
+ * Revision 1.2  2003/07/13 19:43:12  haraldkipp
+ * Ethernut 2.0 support added.
+ *
+ * Revision 1.1.1.1  2003/05/09 14:41:04  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.2  2003/05/06 18:39:37  harald
+ * Realtek definitions
+ *
+ * Revision 1.1  2003/03/31 14:53:23  harald
+ * Prepare release 3.1
+ *
+ */
+
+/*!
+ * \file cfg/ethernut.h
+ * \brief Ethernut hardware specification.
+ *
+ * Including this file is deprecated. Use cfg/arch/avr.h.
+ */
+/*!
+ * \addtogroup xgEthernutCfg
+ */
+/*@{*/
+
+/*! Port output register of \ref RTL_RESET_BIT. */
+#define RTL_RESET_PORT   PORTE
+
+/*! Data direction register of \ref RTL_RESET_BIT. */
+#define RTL_RESET_DDR    DDRE
+
+/*! \brief RTL8019AS hardware reset input.
+
+           Only used on version 1.0 and 1.1 boards. */
+#define RTL_RESET_BIT    4
+
+/*! Port output register of \ref RTL_SIGNAL_BIT. */
+#define RTL_SIGNAL_PORT    PORTE
+
+/*! Port input register of \ref RTL_SIGNAL_BIT. */	
+#define RTL_SIGNAL_PIN     PINE	
+
+/*! Data direction register of \ref RTL_SIGNAL_BIT. */
+#define RTL_SIGNAL_DDR     DDRE	
+
+/*! \brief Interrupt signal handler of \ref RTL_SIGNAL_BIT. */
+#define RTL_SIGNAL  sig_INTERRUPT5
+
+/*! 
+ * \brief Interrupt signal bit for Ethernut 1.x Ethernet controller.
+ */
+#define RTL_SIGNAL_BIT     5
+
+
+/*! 
+ * \brief Ethernut 2.x Ethernet controller base address.
+ */
+#define NIC_BASE            0xC000
+
+/*! Port output register of \ref LAN_SIGNAL_BIT. */
+#define LAN_SIGNAL_PORT     PORTE
+
+/*! Port input register of \ref LAN_SIGNAL_BIT. */	
+#define LAN_SIGNAL_PIN      PINE	
+
+/*! Data direction register of \ref LAN_SIGNAL_BIT. */
+#define LAN_SIGNAL_DDR      DDRE	
+
+/*! \brief Interrupt signal handler of \ref LAN_SIGNAL_BIT. */
+#define LAN_SIGNAL          sig_INTERRUPT5
+
+/*! 
+ * \brief Interrupt signal bit for Ethernut 2.x Ethernet controller.
+ */
+#define LAN_SIGNAL_BIT      5
+
+
+/*@}*/
+
+#endif

include/cfg/fs.h

@@ -0,0 +1,51 @@
+#ifndef _CFG_FS_H_
+#define _CFG_FS_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: fs.h,v $
+ * Revision 1.1  2006/02/23 15:38:59  haraldkipp
+ * PHAT file system now supports configurable number of sector
+ * buffers. This dramatically increased write rates of no-name
+ * cards.
+ *
+ */
+
+/*
+ * This file is reserved for platform independent file system configurations.
+ */
+
+#endif
+

include/cfg/ip.h

@@ -0,0 +1,62 @@
+#ifndef _CFG_IP_H_
+#define _CFG_IP_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/ip.h
+ * \brief IP configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: ip.h,v $
+ * Revision 1.1  2006/09/05 12:35:39  haraldkipp
+ * DHCP servers may probe an IP/MAC relationship by sending an
+ * ICMP request. This triggered the Nut/Net ARP method and
+ * terminated the DHCP client, leaving the system with default
+ * configurations of the network mask (255.255.255.0) and
+ * default gateway (none). The rarely used ARP method is now
+ * disabled by default.
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/lcd.h

@@ -0,0 +1,48 @@
+#ifndef _INCLUDE_CFG_LCD_H_
+#define _INCLUDE_CFG_LCD_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: lcd.h,v $
+ * Revision 1.1  2006/04/07 15:29:04  haraldkipp
+ * First check in
+ *
+ */
+
+/*
+ * This file is reserved for platform independent LCD configurations.
+ */
+
+#endif

include/cfg/m-can.h

@@ -0,0 +1,117 @@
+#ifndef _CFG_MCAN_H_
+#define _CFG_MCAN_H_
+
+/*
+ * Copyright (C) 2004 by Ole Reinhardt<ole.reinhardt@kernelconcepts.de>
+ * Kernel concepts (http://www.kernelconcepts.de) All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: m-can.h,v $
+ * Revision 1.4  2006/10/08 16:48:09  haraldkipp
+ * Documentation fixed
+ *
+ * Revision 1.3  2005/08/02 17:46:48  haraldkipp
+ * Major API documentation update.
+ *
+ * Revision 1.2  2005/05/27 14:08:01  olereinhardt
+ * Changed specs to new m-can board design (LCD controller)
+ *
+ * Revision 1.1  2004/06/07 15:14:25  olereinhardt
+ * Initial checkin
+ *
+ */
+
+/*!
+ * \addtogroup xgMCanCfg
+ */
+/*@{*/
+
+/*!
+ * \file cfg/m-can.h
+ * \brief MCAN Board Configuration
+ */
+
+/*
+ * \brief Defines for CAN controller
+ */
+
+#define SJA_SIGNAL     sig_INTERRUPT7
+#define SJA_EICR       EICRB
+#define SJA_SIGNAL_BIT 7
+
+/*
+ * \brief LCD Display definitions
+ */
+ 
+//#define KS0073_CONTROLLER 
+
+#define LCD_4x20
+
+
+#undef  LCD_DATA_PORT
+#undef  LCD_DATA_DDR
+#undef  LCD_DATA_BITS
+#undef  LCD_DATA_PIN
+
+#define LCD_DATA_PORT   PORTB   /*!< Port output register of \ref LCD_DATA_BITS. */
+#define LCD_DATA_DDR    DDRB    /*!< Data direction register of \ref LCD_DATA_BITS. */
+#define LCD_DATA_BITS   0xFF    /*!< \brief LCD data lines, either upper or lower 4 bits. */
+#define LCD_DATA_PIN    PINB    /*!< Port input register of \ref LCD_DATA_BITS. */
+
+#undef  LCD_ENABLE_PORT
+#undef  LCD_ENABLE_DDR
+#undef  LCD_ENABLE_BIT
+
+#define LCD_ENABLE_PORT PORTE   /*!< Port output register of \ref LCD_ENABLE_BIT. */
+#define LCD_ENABLE_DDR  DDRE    /*!< Data direction register of \ref LCD_ENABLE_BIT. */
+#define LCD_ENABLE_BIT  2       /*!< \brief LCD enable output. */
+
+#undef  LCD_RW_PORT
+#undef  LCD_RW_DDR
+#undef  LCD_RW_BIT
+
+#define LCD_RW_PORT     PORTE   /*!< Port output register of \ref LCD_RW_BIT. */
+#define LCD_RW_DDR      DDRE    /*!< Data direction register of \ref LCD_RW_BIT. */
+#define LCD_RW_BIT      1       /*!< \brief LCD read/write output. */
+
+#undef  LCD_REGSEL_PORT
+#undef  LCD_REGSEL_DDR
+#undef  LCD_REGSEL_BIT
+
+#define LCD_REGSEL_PORT PORTE   /*!< Port output register of \ref LCD_REGSEL_BIT. */
+#define LCD_REGSEL_DDR  DDRE    /*!< Data direction register of \ref LCD_REGSEL_BIT. */
+#define LCD_REGSEL_BIT  0       /*!< \brief LCD register select output. */
+
+/*@}*/
+
+#endif

include/cfg/medianut.h

@@ -0,0 +1,146 @@
+#ifndef _CFG_MEDIANUT_H_
+#define _CFG_MEDIANUT_H_
+
+/*
+ * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: medianut.h,v $
+ * Revision 1.2  2003/07/13 19:42:28  haraldkipp
+ * Infrared remote control added.
+ *
+ * Revision 1.1.1.1  2003/05/09 14:41:04  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.4  2003/05/06 18:39:54  harald
+ * Cleanup
+ *
+ * Revision 1.3  2003/04/07 20:34:06  harald
+ * Oops. Medianut's LCD ports had been accidently removed.
+ *
+ * Revision 1.2  2003/04/07 20:10:37  harald
+ * Redesigned by Pavel Chromy
+ *
+ */
+
+/*!
+ * \file cfg/medianut.h
+ * \brief Medianut hardware specification.
+ */
+
+/*!
+ * \addtogroup xgMedianutCfg
+ */
+/*@{*/
+
+#define VS_SCK_PORT     PORTB	/*!< Port register of \ref VS_SCK_BIT. */
+#define VS_SCK_DDR      DDRB	/*!< Data direction register of \ref VS_SCK_BIT. */
+#define VS_SCK_BIT      0	/*!< \brief VS1001 serial control interface clock input bit. 
+				 * The first rising clock edge after XCS has gone 
+				 * low marks the first bit to be written to the decoder.
+				 */
+
+#define VS_SS_PORT      PORTB	/*!< Port output register of \ref VS_SS_BIT. */
+#define VS_SS_DDR       DDRB	/*!< Data direction register of \ref VS_SS_BIT. */
+#define VS_SS_BIT       1	/*!< \brief VS1001 serial data interface clock input bit. */
+
+#define VS_SI_PORT      PORTB	/*!< Port output register of \ref VS_SI_BIT. */
+#define VS_SI_DDR       DDRB	/*!< Data direction register of \ref VS_SI_BIT. */
+#define VS_SI_BIT       2	/*!< \brief VS1001 serial control interface data input. 
+				 * The decoder samples this input on the 
+				 * rising edge of SCK if XCS is low.
+				 */
+
+#define VS_SO_PIN       PINB	/*!< Port input register of \ref VS_SO_BIT. */
+#define VS_SO_DDR       DDRB	/*!< Data direction register of \ref VS_SO_BIT. */
+#define VS_SO_BIT       3	/*!< \brief VS1001 serial control interface data output. 
+				 * If data is transfered from the decoder, bits
+				 * are shifted out on the falling SCK edge. 
+				 * If data is transfered to the decoder,
+				 * SO is at a high impedance state.
+				 */
+
+#define VS_XCS_PORT     PORTB	/*!< Port output register of \ref VS_XCS_BIT. */
+#define VS_XCS_DDR      DDRB	/*!< Data direction register of \ref VS_XCS_BIT. */
+#define VS_XCS_BIT      4	/*!< \brief VS1001 active low chip select input. 
+				 * A high level forces the serial interface 
+				 * into standby mode, ending the current 
+				 * operation. A high level also forces serial 
+				 * output (SO) to high impedance state.
+				 */
+
+#define VS_BSYNC_PORT   PORTB	/*!< Port output register of \ref VS_BSYNC_BIT. */
+#define VS_BSYNC_DDR    DDRB	/*!< Data direction register of \ref VS_BSYNC_BIT. */
+#define VS_BSYNC_BIT    5	/*!< \brief VS1001 serial data interface bit sync. 
+				 * The first DCLK sampling edge, during 
+				 * which BSYNC is high, marks the first 
+				 * bit of a data byte.
+				 */
+
+#define VS_RESET_PORT   PORTB	/*!< Port output register of \ref VS_RESET_BIT. */
+#define VS_RESET_DDR    DDRB	/*!< Data direction register of \ref VS_RESET_BIT. */
+#define VS_RESET_BIT    7	/*!< \brief VS1001 hardware reset input. */
+
+#define VS_DREQ_PORT    PORTE	/*!< Port output register of \ref VS_DREQ_BIT. */
+#define VS_DREQ_PIN     PINE	/*!< Port input register of \ref VS_DREQ_BIT. */
+#define VS_DREQ_DDR     DDRE	/*!< Data direction register of \ref VS_DREQ_BIT. */
+#define VS_DREQ_BIT     6	/*!< \brief VS1001 data request output. */
+
+
+
+#define LCD_DATA_PORT   PORTD   /*!< Port output register of \ref LCD_DATA_BITS. */
+#define LCD_DATA_DDR    DDRD    /*!< Data direction register of \ref LCD_DATA_BITS. */
+#define LCD_DATA_BITS   0xF0    /*!< \brief LCD data lines, either upper or lower 4 bits. */
+
+#define LCD_ENABLE_PORT PORTE   /*!< Port output register of \ref LCD_ENABLE_BIT. */
+#define LCD_ENABLE_DDR  DDRE    /*!< Data direction register of \ref LCD_ENABLE_BIT. */
+#define LCD_ENABLE_BIT  3       /*!< \brief LCD enable output. */
+
+#define LCD_REGSEL_PORT PORTE   /*!< Port output register of \ref LCD_REGSEL_BIT. */
+#define LCD_REGSEL_DDR  DDRE    /*!< Data direction register of \ref LCD_REGSEL_BIT. */
+#define LCD_REGSEL_BIT  2       /*!< \brief LCD register select output. */
+
+#define LCD_LIGHT_PORT  PORTB   /*!< Port output register of \ref LCD_LIGHT_BIT. */
+#define LCD_LIGHT_DDR   DDRB    /*!< Data direction register of \ref LCD_LIGHT_BIT. */
+#define LCD_LIGHT_BIT   6       /*!< \brief LCD output to switch backlight. */
+
+#define IR_SIGNAL_PORT  PORTE   /*!< Port output register of \ref IR_SIGNAL_BIT. */
+#define IR_SIGNAL_PIN   PINE    /*!< Port input register of \ref IR_SIGNAL_BIT. */
+#define IR_SIGNAL_DDR   DDRE    /*!< Data direction register of \ref IR_SIGNAL_BIT. */
+#define IR_SIGNAL_BIT   4       /*!< \brief Infrared decoder signal bit. */
+
+/*@}*/
+
+
+#endif
+

include/cfg/memory.h

@@ -0,0 +1,136 @@
+#ifndef _CFG_MEMORY_H_
+#define _CFG_MEMORY_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: memory.h,v $
+ * Revision 1.1  2004/08/25 10:56:10  haraldkipp
+ * More general memory layout definitions moved from cfg/bankmem.h to cfg/memory.h.
+ *
+ */
+
+/*!
+ * \file cfg/memory.h
+ * \brief Default memory layout.
+ *
+ * Values can be changed by the configurator.
+ */
+
+#ifndef NUTMEM_SIZE
+/*!
+ * \brief Number of bytes available in fast data memory.
+ *
+ * On most platforms this value specifies the total number of bytes 
+ * available in RAM. 
+ *
+ * On Harvard architectures this value specifies the size of the data 
+ * memory. It will be occupied by global variables and static data. 
+ * Any remaining space will be added to the Nut/OS heap during system 
+ * initialization.
+ *
+ */
+#define NUTMEM_SIZE 4096
+#endif
+
+#ifndef NUTMEM_START
+/*!
+ * \brief First address of fast data memory.
+ */
+#define NUTMEM_START 0x100
+#endif
+
+#ifndef NUTMEM_RESERVED
+/*!
+ * \brief Number of bytes reserved for special purposes.
+ *
+ * Right now this is used with the AVR platform only. The specified 
+ * number of bytes may be used by a device driver when the external 
+ * memory interface is disabled.
+ */
+#define NUTMEM_RESERVED 64
+#endif
+
+#ifndef NUTXMEM_SIZE
+/*!
+ * \brief Number of bytes available in extended data memory.
+ */
+#define NUTXMEM_SIZE 28416
+#endif
+
+#ifndef NUTXMEM_START
+/*
+ * \brief First address of extended data memory.
+ */
+#define NUTXMEM_START 0x1100
+#endif
+
+#ifndef NUTBANK_COUNT
+/*!
+ * \brief Number of memory banks.
+ *
+ * For systems without banked memory this is set to zero.
+ * Ethernut 2 has 30 memory banks.
+ */
+#define NUTBANK_COUNT   0
+#endif
+
+#ifndef NUTBANK_START
+/*!
+ * \brief Start address of memory banks.
+ *
+ * For systems without banked memory this is ignored.
+ */
+#define NUTBANK_START   0x8000
+#endif
+
+#ifndef NUTBANK_SIZE
+/*!
+ * \brief Size of a single memory bank.
+ *
+ * For systems without banked memory this is ignored.
+ */
+#define NUTBANK_SIZE    0x4000
+#endif
+
+#ifndef NUTBANK_SR
+/*!
+ * \brief Address of the bank select register.
+ *
+ * For systems without banked memory this is ignored.
+ */
+#define NUTBANK_SR      0xFF00
+#endif
+
+#endif

include/cfg/modem.h

@@ -0,0 +1,159 @@
+#ifndef _CFG_MODEM_H_
+#define _CFG_MODEM_H_
+
+/*
+ * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: modem.h,v $
+ * Revision 1.5  2005/04/19 09:02:17  haraldkipp
+ * Ole's mishap repaired
+ *
+ * Revision 1.5  2005/01/22 19:26:34  haraldkipp
+ * Marked deprecated.
+ *
+ * Revision 1.4  2004/03/08 11:17:58  haraldkipp
+ * Hardware handshake disabled by default.
+ *
+ * Revision 1.3  2003/12/15 19:27:11  haraldkipp
+ * Ethernut 2 handshake lines
+ *
+ * Revision 1.2  2003/08/05 20:17:46  haraldkipp
+ * Typing errors corrected
+ *
+ * Revision 1.1.1.1  2003/05/09 14:41:04  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.1  2003/05/06 18:37:33  harald
+ * *** empty log message ***
+ *
+ */
+
+/*!
+ * \file cfg/modem.h
+ * \brief RS232 handshake hardware specification.
+ *
+ * Including this file is deprecated. Use cfg/arch/avr.h.
+ */
+
+/*!
+ * \addtogroup xgModemCfg
+ */
+/*@{*/
+
+#if 0
+
+/*! Port output register of \ref UART0_RTS_BIT. */
+#define UART0_RTS_PORT  PORTE
+/*! Data direction register of \ref UART0_RTS_BIT. */
+#define UART0_RTS_DDR   DDRE
+/*! \brief RTS handshake control bit.
+ *
+ * If undefined, RTS handshake is not supported. 
+ */
+#define UART0_RTS_BIT   2
+
+
+/*! Port output register of \ref UART0_CTS_BIT. */
+#define UART0_CTS_PORT   PORTE
+/*! Port input register of \ref UART0_CTS_BIT. */
+#define UART0_CTS_PIN    PINE
+/*! Data direction register of \ref UART0_CTS_BIT. */
+#define UART0_CTS_DDR    DDRE
+/*! Interrupt signal of \ref UART0_CTS_BIT. */
+#define UART0_CTS_SIGNAL sig_INTERRUPT7
+/*! \brief CTS handshake sense bit.
+ *
+ * If undefined, CTS handshake is not supported. 
+ */
+#define UART0_CTS_BIT    7
+
+
+/*! Port output register of \ref UART0_HDX_BIT. */
+#define UART0_HDX_PORT  PORTD
+/*! Data direction register of \ref UART0_HDX_BIT. */
+#define UART0_HDX_DDR   DDRD
+/*! \brief Half duplex control bit.
+ *
+ * If undefined, half duplex is not supported. 
+ */
+#define UART0_HDX_BIT   4
+
+#endif
+
+
+#if 0
+
+/*! Port output register of \ref UART1_RTS_BIT. */
+#define UART1_RTS_PORT   PORTD
+/*! Data direction register of \ref UART1_RTS_BIT. */
+#define UART1_RTS_DDR    DDRD
+/*! \brief RTS handshake output bit.
+ * 
+ * If undefined, RTS handshake is not supported. 
+ */
+#define UART1_RTS_BIT    5
+
+
+/*! Port output register of \ref UART1_CTS_BIT. */
+#define UART1_CTS_PORT   PORTE
+/*! Port input register of \ref UART1_CTS_BIT. */
+#define UART1_CTS_PIN    PINE
+/*! Data direction register of \ref UART1_CTS_BIT. */
+#define UART1_CTS_DDR    DDRE
+/*! Interrupt signal of \ref UART1_CTS_BIT. */
+#define UART1_CTS_SIGNAL sig_INTERRUPT7
+/*! \brief CTS handshake input bit. 
+ *
+ * If undefined, CTS handshake is not supported.
+ * Bits 0 to 3 are not supported. 
+ */
+#define UART1_CTS_BIT    7
+
+
+/*! Port output register of \ref UART1_DTR_BIT. */
+#define UART1_DTR_PORT   PORTD
+/*! Data direction register of \ref UART1_DTR_BIT. */
+#define UART1_DTR_DDR    DDRD
+/*! \brief DTR handshake output bit.
+ *
+ * If undefined, DTR handshake is not supported. 
+ */
+#define UART1_DTR_BIT    7
+
+#endif
+
+
+/*@}*/
+
+#endif

include/cfg/os.h

@@ -0,0 +1,61 @@
+#ifndef _CFG_OS_H_
+#define _CFG_OS_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: os.h,v $
+ * Revision 1.2  2004/11/08 18:58:59  haraldkipp
+ * Configurable stack sizes
+ *
+ * Revision 1.1  2004/09/19 12:31:52  haraldkipp
+ * Configuration placeholders added
+ *
+ */
+
+/*
+ * This file is reserved for kernel related configurations.
+ *
+ */
+
+#ifndef NUT_THREAD_MAINSTACK
+#define NUT_THREAD_MAINSTACK    768
+#endif
+
+#ifndef NUT_THREAD_IDLESTACK
+#define NUT_THREAD_IDLESTACK    384
+#endif
+
+#endif
+

include/cfg/ppp.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_PPP_H_
+#define _CFG_PPP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/ppp.h
+ * \brief PPP driver configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: ppp.h,v $
+ * Revision 1.1  2005/04/05 17:46:24  haraldkipp
+ * Initial check in.
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/progif.h

@@ -0,0 +1,48 @@
+#ifndef _CFG_PROGIF_H_
+#define _CFG_PROGIF_H_
+
+/*
+ * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: progif.h,v $
+ * Revision 1.1  2007/04/12 09:01:40  haraldkipp
+ * New API allows to program external AVR devices.
+ *
+ */
+
+/*
+ * This file is reserved for platform independent programming configurations.
+ */
+
+#endif

include/cfg/rport.h

@@ -0,0 +1,101 @@
+#ifndef _CFG_RPORT_H_
+#define _CFG_RPORT_H_
+
+/*
+ * Copyright (C) 2004 by Jan Dubiec. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JAN DUBIEC AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JAN DUBIEC
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $Log: rport.h,v $
+ * Revision 1.1  2004/03/16 16:56:21  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ */
+
+/*!
+ * \file cfg/rport.h
+ * \brief RPort hardware specification.
+ */
+/*!
+ * \addtogroup xgRPortCfg
+ */
+/*@{*/
+
+#include <h83068f.h>
+
+/*!
+ * Low level sensing interrupt; Very important!
+ * High poriority;
+ * CKE1-0 in SCR, default setting;
+ * C/A# in SMR, default setting;
+ * P95DDR, default setting:
+ * P9DDR = B_1100_0000;
+ * SCI1.SMR.BIT.CA = 0;
+ */
+#define NutInitSysIrq()                 \
+    INTC.ISCR.BIT.IRQ0SC = 0;           \
+    INTC.IPRA.BIT._IRQ0  = 0; 
+
+/** 
+ * IO base address of RTL chip.
+ */
+#define NIC_IO_BASE     (0x800000UL + 0x300UL)
+
+/**
+ * Check Nic Int is set or not
+ */
+#define NicIntIsEnabled()  (INTC.IER.BIT.IRQ0E == 1)
+
+/**
+ * Disable Nic Interruption
+ */
+#define NicDisableInt() INTC.IER.BIT.IRQ0E = 0
+
+/**
+ * Enable Nic Interruption
+ */
+#define NicEnableInt()  INTC.IER.BIT.IRQ0E = 1
+
+/**
+ * Switch MCU data bus (area 4) into 16 bit mode
+ */
+#define NicMcu16bitBus() BSC.ABWCR.BIT.ABW4 = 0
+
+/**
+ * Switch MCU data bus (area 4) into 8 bit mode
+ */
+#define NicMcu8bitBus() BSC.ABWCR.BIT.ABW4 = 1
+
+/**
+ * interruption signal handler of RTL_SIGNAL_BIT. 
+ */
+#define RTL_SIGNAL      sig_INT0
+
+/*@}*/
+
+#endif /* #ifndef _CFG_RPORT_H_ */

include/cfg/sntp.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_SNTP_H_
+#define _CFG_SNTP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/sntp.h
+ * \brief SNTP client configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: sntp.h,v $
+ * Revision 1.1  2005/04/05 17:46:24  haraldkipp
+ * Initial check in.
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/syslog.h

@@ -0,0 +1,50 @@
+#ifndef _CFG_SYSLOG_H_
+#define _CFG_SYSLOG_H_
+
+/*
+ * Copyright (C) 2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: syslog.h,v $
+ * Revision 1.1  2004/09/19 12:31:52  haraldkipp
+ * Configuration placeholders added
+ *
+ */
+
+/*
+ * This file is reserved for syslog related configurations.
+ *
+ */
+
+#endif
+

include/cfg/tcp.h

@@ -0,0 +1,57 @@
+#ifndef _CFG_TCP_H_
+#define _CFG_TCP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * \file cfg/tcp.h
+ * \brief TCP configuration.
+ *
+ * This is used only when building the system in the source tree. If the 
+ * Configurator is used, a file with the same name will be created in the 
+ * build tree, which replaces this file.
+ *
+ * \verbatim
+ *
+ * $Log: tcp.h,v $
+ * Revision 1.1  2005/04/05 17:46:24  haraldkipp
+ * Initial check in.
+ *
+ *
+ * \endverbatim
+ */
+
+
+#endif
+

include/cfg/twi.h

@@ -0,0 +1,49 @@
+#ifndef _INCLUDE_CFG_TWI_H_
+#define _INCLUDE_CFG_TWI_H_
+
+/*
+ * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*!
+ * $Log: twi.h,v $
+ * Revision 1.1  2007/02/15 16:17:28  haraldkipp
+ * Configurable port bits for bit-banging I2C. Should work now on all
+ * AT91 MCUs.
+ *
+ */
+
+/*
+ * This file is reserved for platform independent TWI configurations.
+ */
+
+#endif

include/cfg/xnut.h

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2005 FOCUS Software Engineering Pty Ltd <www.focus-sw.com>
+ * Copyright (c) 2005 proconX <www.proconx.com>
+ *
+ * $Id: xnut.h,v 1.2 2005/10/19 09:27:39 hwmaier Exp $
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+
+#ifndef _CFG_XNUT_H_
+#define _CFG_XNUT_H_
+
+#ifndef _XNUT_XXX_H_INCLUDED
+#  define _XNUT_XXX_H_INCLUDED "cfg/xnut.h"
+#else
+#  error "Attempt to include more than one <xnut-xxx.h> file"
+#endif
+
+
+#include <cfg/os.h>
+#include <cfg/memory.h>
+#include <cfg/arch.h>
+#include <cfg/eeprom.h>
+#include <arch/avr.h>
+#include <cfg/arch/avrpio.h>
+
+/* Validate F_CPU setting */
+#if F_CPU == 1000000UL
+#  error "F_CPU is set to avr-lib default 1 MHz! Please include <avr/delay.h> after <xnut.h>"
+#endif
+#define F_CPU NUT_CPU_FREQ
+
+
+/*!
+ * \defgroup xgXnutCfg XNUT-100 & XNUT-105 DIN-rail SBC
+ * \ingroup xgConfigAvr
+ * \brief DIN-rail mounted Single Board Computer in enclosure with
+ * 2 x RS-232, 2 x RS-485, 1 x RS-422 interfaces (software configurable),
+ * CAN port (XNUT-105) and 10-30 V (24 V) switch mode power supply.
+ * The <A href="http://www.proconx.com/xnut100">XNUT-100</A> and
+ * <A href="http://www.proconx.com/xnut105">XNUT-105</A>
+ * modules have been specifically designed for industrial communication
+ * tasks such as Monitoring & Controlling serial devices,
+ * gathering sensor data, Gateway Applications and Protocol Conversion.
+ */
+//@{
+
+/*****************************************************************************
+ * LED control macros
+ *****************************************************************************/
+
+/**
+ * @defgroup xnutLed LED Control Macros
+ *
+ * @brief Functions to drive the XNUT status LED S1 (LED3) and S2 (LED4).
+ */
+//@{
+
+/** Switch LED S1 off */
+#define LED_S1_OFF()         PORTF &= ~_BV(2); PORTF &= ~_BV(3);
+/** Switch LED S1 red */
+#define LED_S1_RED()         PORTF &= ~_BV(2); PORTF |= _BV(3);
+/** Switch LED S1 green */
+#define LED_S1_GREEN()       PORTF |= _BV(2); PORTF &= ~_BV(3);
+
+/** Switch LED S2 off */
+#define LED_S2_OFF()         PORTF &= ~_BV(0); PORTF &= ~_BV(1);
+/** Switch LED S2 red */
+#define LED_S2_RED()         PORTF &= ~_BV(0); PORTF |= _BV(1);
+/** Switch LED S2 green */
+#define LED_S2_GREEN()       PORTF |= _BV(0); PORTF &= ~_BV(1);
+
+//@}
+
+
+/*****************************************************************************
+ * UART control macros
+ *****************************************************************************/
+
+/**
+ * @defgroup xnutSer UART Control Macros
+ *
+ * @brief Functions to control UART modes
+ */
+//@{
+
+/**
+ * Configure Ser 0 to operate in RS232 mode.
+ *
+ * In RS232 mode receiption from SUB-D connector J9 is enabled
+ * and the receiver on connector J6-2/3 is disabled.
+ */
+#define SER0_RS232_MODE()    (PORTB |= _BV(0))
+
+/**
+ * Configure Ser 0 to operate in RS485 mode.
+ *
+ * In RS485 mode receiption from connector J6-2/3 is enabled
+ * and the receiver on SUB-D connector J9 is disabled.
+ */
+#define SER0_RS485_MODE()    (PORTB &= ~_BV(0))
+
+/**
+ * Switches the RS485 line driver of Ser 0 on.
+ *
+ * RS485 is a half-duplex link and the line driver must be switched off to
+ * allow receiption of data.
+ */
+#define SER0_RS485_DRV_ON()   (PORTB |= _BV(1))
+
+/**
+ * Switches the RS485 line driver of Ser 0 off.
+ */
+#define SER0_RS485_DRV_OFF()  (PORTB &= ~_BV(1))
+
+/**
+ * Configure Ser 1 to operate in RS232 mode.
+ *
+ * In RS232 mode receiption from SUB-D connector J7 is enabled
+ * and the receiver on connector J6-5/6 is disabled.
+ */
+#define SER1_RS232_MODE()    (PORTB |= _BV(2))
+
+/**
+ * Configure Ser 1 to operate in RS485 mode.
+ *
+ * In RS485 mode receiption from connector J6-5/6 is enabled
+ * and the receiver on SUB-D connector J7 is disabled.
+ */
+#define SER1_RS485_MODE()    (PORTB &= ~_BV(2))
+
+/**
+ * Switches the RS485 line driver of Ser 1 on.
+ *
+ * RS485 is a half-duplex link and the line driver must be switched off to
+ * allow receiption of data.
+ */
+#define SER1_RS485_DRV_ON()   (PORTB |= _BV(3))
+
+/**
+ * Switches the RS485 line driver of Ser 1 off.
+ */
+#define SER1_RS485_DRV_OFF()  (PORTB &= ~_BV(3))
+
+/**
+ * Returns the status of the RS232 CD signal input
+ * of Ser 0 on SUB-D connector J9
+ *
+ * @return 1 if CD is asserted
+ */
+#define SER0_GET_CD()        bit_is_set(PINB, 6)
+
+/**
+ * Returns the status of the RS232 RI signal input
+ * of Ser 0 on SUB-D connector J9
+ *
+ * @return 1 if RI is asserted
+ */
+#define SER0_GET_RI()        bit_is_set(PINB, 7)
+
+/**
+ * Returns the status of the RS232 CTS signal input
+ * of Ser 0 on SUB-D connector J9
+ *
+ * @return 1 if CTS is asserted
+ */
+#define SER0_GET_CTS()       bit_is_set(PINE, 6)
+
+/**
+ * Asserts the RS232 RTS signal output of Ser 0 on SUB-D connector J9
+ */
+#define SER0_SET_RTS()       (PORTB |= _BV(4))
+
+/**
+ * Clears the RS232 RTS signal output of Ser 0 on SUB-D connector J9
+ */
+#define SER0_CLR_RTS()       (PORTB &= ~_BV(4))
+
+//@}
+
+//@}
+
+#endif // ifdef ..._H_INCLUDED
+

include/compiler.h

@@ -0,0 +1,81 @@
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+/*
+ * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: compiler.h,v $
+ * Revision 1.11  2005/08/02 17:46:47  haraldkipp
+ * Major API documentation update.
+ *
+ * Revision 1.10  2005/07/26 15:49:59  haraldkipp
+ * Cygwin support added.
+ *
+ * Revision 1.9  2005/02/10 07:06:50  hwmaier
+ * Changes to incorporate support for AT90CAN128 CPU
+ *
+ * Revision 1.8  2004/04/07 12:13:57  haraldkipp
+ * Matthias Ringwald's *nix emulation added
+ *
+ * Revision 1.7  2004/03/18 15:51:45  haraldkipp
+ * ICCAVR failed to compile
+ *
+ * Revision 1.6  2004/03/16 16:48:27  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ * Revision 1.5  2004/02/01 18:49:47  haraldkipp
+ * Added CPU family support
+ *
+ */
+
+#ifdef  __cplusplus
+# define __BEGIN_DECLS  extern "C" {
+# define __END_DECLS    }
+#else
+# define __BEGIN_DECLS
+# define __END_DECLS
+#endif
+
+#if defined(__AVR__) || defined(ATMEGA)
+#include <arch/avr.h>
+#elif defined(__arm__)
+#include <arch/arm.h>
+#elif defined(__H8300__) || defined(__H8300H__) || defined(__H8300S__)
+#include <arch/h8.h>
+#elif defined(__m68k__)
+#include <arch/m68k.h>
+#elif defined(__linux__) || defined (__APPLE__) || defined(__CYGWIN__)
+#include <arch/unix.h>
+#endif
+
+#endif

include/cpp/nutcpp.h

@@ -0,0 +1,87 @@
+#ifndef _NUTCPP_H_
+#define _NUTCPP_H_
+
+/*
+ * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+
+/*
+ * $Log: nutcpp.h,v $
+ * Revision 1.2  2006/07/10 14:28:06  haraldkipp
+ * Defined functions for new and delete operator.
+ *
+ * Revision 1.1  2005/01/22 19:10:54  haraldkipp
+ * Added C++ support contributed by Oliver Schulz (MPI).
+ *
+ *
+ */
+
+
+
+#if defined(__cplusplus)
+
+// ====================================================================
+
+#include <compiler.h>
+#include <stdlib.h>
+
+// == Adapt NutOS main() hack for gcc to C++ ==================================
+
+#if defined(__GNUC__) && defined(main)
+
+#undef main
+#define main    _cxx_main_
+#define _cxx_pre_main_    NutAppMain
+
+int main(void);
+
+#endif // defined(__cplusplus) && defined(__GNUC__) && defined(main)
+
+
+// == Define new and delete if needed =================================
+
+#if defined(__GNUC__) && ((defined(__AVR) || defined(__arm__)))
+//inline void * operator new(unsigned int s) {
+inline void * operator new(size_t s) {
+    return malloc(s);
+}
+
+inline void operator delete(void *m) {
+    free(m);
+}
+#endif // defined(__GNUC__) && defined(__AVR)
+
+
+// ====================================================================
+
+#endif // defined(__cplusplus)
+#endif // _NUTCPP_H_

include/cpu_load.h

@@ -0,0 +1,16 @@
+/*
+ * <MFS> Modified for Streamit
+ * File added for CPU-load measurements
+ *
+ * Copyright (C) 2007 by Streamit BV. All rights reserved.
+ */
+
+#ifndef _CPU_LOAD_H_
+#define _CPU_LOAD_H_
+
+//#define CPU_LOAD_MEASURE
+#define CPU_LOAD_PORT PORTE
+#define CPU_LOAD_BIT 3
+#define CPU_LOAD_DDR DDRE
+
+#endif

include/dev/ace.h

@@ -0,0 +1,451 @@
+#ifndef _DEV_ACE_H
+#define _DEV_ACE_H
+
+/*
+ * Copyright (C) 2001-2003 by Cyber Integration, LLC. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CYBER INTEGRATION, LLC AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL CYBER
+ * INTEGRATION, LLC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *
+ */
+
+/*
+ * $Log: ace.h,v $
+ * Revision 1.2  2006/05/25 09:09:57  haraldkipp
+ * API documentation updated and corrected.
+ *
+ * Revision 1.1  2005/11/24 11:24:06  haraldkipp
+ * Initial check-in.
+ * Many thanks to William Basser for this code and also to Przemyslaw Rudy
+ * for several enhancements.
+ *
+ */
+
+#include <sys/device.h>
+
+/*!
+ * \file dev/ace.h
+ * \brief ACE I/O function prototypes.
+ */
+
+/*!
+ * \addtogroup xgAceDriver
+ *
+ * \brief ACE _ioctl() commands.
+ *
+ * These commands are used to control and retrieve hardware specific
+ * configurations. The definitions are kept independent from the 
+ * underlying hardware, but not all commands may be fully implemented 
+ * in each ACE driver.
+ *
+ * The _ioctl() function expects three parameters:
+ * - A device descriptor.
+ * - A command code, any of the ACE_... commands listed below.
+ * - A pointer to a configuration parameter, in most cases an unsigned long.
+ */
+/*@{*/
+
+/*! \brief ACE _ioctl() command code to set the line speed.
+ *
+ * The configuration parameter specifies the input and output bit rate 
+ * per second.
+ */
+#define ACE_SETSPEED           0x0101
+
+/*! \brief ACE _ioctl() command code to query the line speed.
+ *
+ * The configuration parameter is set to the input and output bit rate 
+ * per second.
+ */
+#define ACE_GETSPEED           0x0102
+
+/*! \brief ACE _ioctl() command code to set the number of data bits.
+ *
+ * The configuration parameter specifies the number of data bits, 5, 6, 
+ * 7, 8 or 9.
+ */
+#define ACE_SETDATABITS        0x0103
+
+/*! \brief ACE _ioctl() command code to query the number of data bits.
+ *
+ * The configuration parameter is set to the number of data bits, 5, 6, 
+ * 7, 8 or 9.
+ */
+#define ACE_GETDATABITS        0x0104
+
+/*! \brief ACE _ioctl() command code to set the parity mode.
+ *
+ * The configuration parameter specifies the type of the parity bit, 
+ * 0 (none), 1 (odd), 2 (even), 3 (mark) or 4 (space).
+ */
+#define ACE_SETPARITY          0x0105
+
+/*! \brief ACE _ioctl() command code to query the parity mode.
+ *
+ * The configuration parameter is set to the type of the parity bit, 
+ * 0 (none), 1 (odd), 2 (even), 3 (mark) or 4 (space).
+ */
+#define ACE_GETPARITY          0x0106
+
+/*! \brief ACE _ioctl() command code to set the number of stop bits.
+ *
+ * The configuration parameter specifies the number of stop bits, 1 or 2.
+ */
+#define ACE_SETSTOPBITS        0x0107
+
+/*! \brief ACE _ioctl() command code to query the number of stop bits.
+ *
+ * The configuration parameter is set to the number of stop bits, 1 or 2.
+ */
+#define ACE_GETSTOPBITS        0x0108
+
+/*! \brief ACE _ioctl() command code to set the status.
+ *
+ * The configuration parameter specifies the status to set.
+ */
+#define ACE_SETSTATUS          0x0109
+
+/*! \brief ACE _ioctl() command code to query the status.
+ *
+ * The configuration parameter is set to the current status.
+ */
+#define ACE_GETSTATUS          0x010a
+
+/*! \brief ACE _ioctl() command code to set the read timeout.
+ *
+ * The configuration parameter specifies the read timeout in 
+ * milliseconds.
+ */
+#define ACE_SETREADTIMEOUT     0x010b
+
+/*! \brief ACE _ioctl() command code to query the read timeout.
+ *
+ * The configuration parameter is set to the read timeout in 
+ * milliseconds.
+ */
+#define ACE_GETREADTIMEOUT     0x010c
+
+/*! \brief ACE _ioctl() command code to set the write timeout.
+ *
+ * The configuration parameter specifies the write timeout in 
+ * milliseconds.
+ */
+#define ACE_SETWRITETIMEOUT    0x010d
+
+/*! \brief ACE _ioctl() command code to query the write timeout.
+ *
+ * The configuration parameter is set to the write timeout in 
+ * milliseconds.
+ */
+#define ACE_GETWRITETIMEOUT    0x010e
+
+/*! \brief ACE _ioctl() command code to set the local echo mode.
+ *
+ * The configuration parameter specifies the local echo mode, 
+ * 0 (off) or 1 (on).
+ */
+#define ACE_SETLOCALECHO       0x010f
+
+/*! \brief ACE _ioctl() command code to query the local echo mode.
+ *
+ * The configuration parameter is set to the local echo mode, 
+ * 0 (off) or 1 (on).
+ */
+#define ACE_GETLOCALECHO       0x0110
+
+/*! \brief ACE _ioctl() command code to set the flow control mode.
+ *
+ * The configuration parameter specifies the flow control mode.
+ */
+#define ACE_SETFLOWCONTROL     0x0111
+
+/*! \brief ACE _ioctl() command code to query the flow control mode.
+ *
+ * The configuration parameter is set to the flow control mode.
+ */
+#define ACE_GETFLOWCONTROL     0x0112
+
+/*! \brief ACE _ioctl() command code to set the cooking mode.
+ *
+ * The configuration parameter specifies the character cooking mode, 
+ * 0 (raw) or 1 (EOL translation).
+ */
+#define ACE_SETCOOKEDMODE      0x0113
+
+/*! \brief ACE _ioctl() command code to query the cooking mode.
+ *
+ * The configuration parameter is set to the character cooking mode, 
+ * 0 (raw) or 1 (EOL translation).
+ */
+#define ACE_GETCOOKEDMODE      0x0114
+
+/*! \brief ACE _ioctl() command code to set the buffering mode.
+ *
+ * The configuration parameter specifies the buffering mode.
+ */
+#define ACE_SETBUFFERMODE      0x0115
+
+/*! \brief ACE _ioctl() command code to query the buffering mode.
+ *
+ * The configuration parameter is set to the buffering mode.
+ */
+#define ACE_GETBUFFERMODE      0x0116
+
+/*! \brief ACE _ioctl() command code to set the transmit buffer size.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETTXBUFSIZ        0x011b
+
+/*! \brief ACE _ioctl() command code to query the transmit buffer size.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETTXBUFSIZ        0x011c
+
+/*! \brief ACE _ioctl() command code to set the receive buffer size.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETRXBUFSIZ        0x011d
+
+/*! \brief ACE _ioctl() command code to query the receive buffer size.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETRXBUFSIZ        0x011e
+
+/*! \brief ACE _ioctl() command code to set the transmit buffer low watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETTXBUFLWMARK     0x0120
+
+/*! \brief ACE _ioctl() command code to query the transmit buffer low watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETTXBUFLWMARK     0x0121
+
+/*! \brief ACE _ioctl() command code to set the transmit buffer high watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETTXBUFHWMARK     0x0122
+
+/*! \brief ACE _ioctl() command code to query the transmit buffer high watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETTXBUFHWMARK     0x0123
+
+/*! \brief ACE _ioctl() command code to set the receive buffer low watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETRXBUFLWMARK     0x0124
+
+/*! \brief ACE _ioctl() command code to query the receive buffer low watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETRXBUFLWMARK     0x0125
+
+/*! \brief ACE _ioctl() command code to set the receive buffer high watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_SETRXBUFHWMARK     0x0126
+
+/*! \brief ACE _ioctl() command code to query the receive buffer high watermark.
+ *
+ * The configuration parameter specifies the number of bytes.
+ */
+#define ACE_GETRXBUFHWMARK     0x0127
+
+/*! \brief ACE _ioctl() command code to set the block read mode
+*
+* The configuration parameter specifies the block read mode
+*/
+#define ACE_SETBLOCKREAD		0x0128
+
+/*! \brief ACE _ioctl() command code to query the receive buffer high watermark.
+*
+* The configuration parameter specifies the block read mode
+*/
+#define ACE_GETBLOCKREAD		0x0129
+
+/*! \brief ACE _ioctl() command code to set the fifo mode and receive fifo trigger level.
+*
+* The configuration parameter specifies the receive fifo trigger level (x,1,4,8,14), x - disables fifo
+*/
+#define ACE_SETFIFO		0x012a
+
+/*! \brief ACE _ioctl() command code to query the fifo mode and receive fifo trigger level.
+*
+* The configuration parameter specifies the receive fifo trigger level (x,1,4,8,14), x - fifo is disabled
+*/
+#define ACE_GETFIFO		0x012b
+
+/*!
+ * \addtogroup xgACEStatus
+ * \brief ACE device status flags,
+ *
+ * A combination of these status flags is used by the _ioctl() commands
+ * \ref ACE_SETSTATUS and \ref ACE_GETSTATUS. 
+ */
+/*@{*/
+
+/*! \brief Framing error.
+ *
+ * \ref ACE_SETSTATUS will clear this error.
+ */
+#define ACE_FRAMINGERROR   0x00000001UL
+
+/*! \brief Overrun error. 
+ *
+ * \ref ACE_SETSTATUS will clear this error.
+ */
+#define ACE_OVERRUNERROR   0x00000002UL
+
+/*! \brief Parity error. 
+ *
+ * \ref ACE_SETSTATUS will clear this error.
+ */
+#define ACE_PARITYERROR    0x00000004UL
+
+/*! \brief ACE errors.
+ *
+ * \ref ACE_SETSTATUS will clear all errors.
+ */
+#define ACE_ERRORS         (ACE_FRAMINGERROR | ACE_OVERRUNERROR | ACE_PARITYERROR)
+
+/*! \brief Receiver buffer empty. 
+ */
+#define ACE_RXBUFFEREMPTY  0x00000040UL
+
+/*! \brief Transmitter buffer empty.
+ *
+ * \ref ACE_SETSTATUS will immediately clear the buffer. It will not 
+ * wait until the remaining characters have been transmitted.
+ */
+#define ACE_TXBUFFEREMPTY  0x00000080UL
+
+/*! \brief RTS handshake output enabled. 
+ */
+#define ACE_RTSENABLED     0x00000100UL
+
+/*! \brief RTS handshake output disabled. 
+ */
+#define ACE_RTSDISABLED    0x00000200UL
+
+/*! \brief CTS handshake input enabled. 
+ */
+#define ACE_CTSENABLED     0x00000400UL
+
+/*! \brief CTS handshake input disabled. 
+ */
+#define ACE_CTSDISABLED    0x00000800UL
+
+/*! \brief DTR handshake output enabled. 
+ */
+#define ACE_DTRENABLED     0x00001000UL
+
+/*! \brief DTR handshake output disabled. 
+ */
+#define ACE_DTRDISABLED    0x00002000UL
+
+/*! \brief Receiver enabled. 
+ */
+#define ACE_RXENABLED      0x00010000UL
+
+/*! \brief Receiver enabled. 
+ */
+#define ACE_RXDISABLED     0x00020000UL
+
+/*! \brief Transmitter enabled. 
+ */
+#define ACE_TXENABLED      0x00040000UL
+
+/*! \brief Transmitter enabled. 
+ */
+#define ACE_TXDISABLED     0x00080000UL
+
+/*@}*/
+
+/*!
+ * \addtogroup xgACEHS
+ * \brief ACE handshake modes.
+ *
+ * Any of these values may be used by the _ioctl() commands
+ * \ref ACE_SETFLOWCONTROL and \ref ACE_GETFLOWCONTROL.
+ */
+/*@{*/
+
+/*! \brief RTS / CTS hardware handshake.
+ *
+ * Nut/OS uses DTE definitions, where RTS is output and CTS is input.
+ */
+#define ACE_HS_RTSCTS      0x0003
+
+/*! \brief Full modem hardware handshake.
+ *
+ * Not supported yet by the standard drivers.
+ */
+#define ACE_HS_MODEM       0x001F
+
+/*! \brief XON / XOFF software handshake.
+ *
+ * It is recommended to set a proper read timeout with software handshake.
+ * In this case a timeout may occur, if the communication peer lost our 
+ * last XON character. The application may then use ioctl() to disable the 
+ * receiver and do the read again. This will send out another XON.
+ */
+#define ACE_HS_SOFT        0x0020
+
+/*@}*/
+
+__BEGIN_DECLS
+/* */
+extern int AceInit(NUTDEVICE * dev);
+extern int AceIOCtl(NUTDEVICE * dev, int req, void *conf);
+extern int AceInput(NUTDEVICE * dev);
+extern int AceOutput(NUTDEVICE * dev);
+extern int AceFlush(NUTDEVICE * dev);
+
+extern int AceGetRaw(u_char * cp);
+extern int AcePutRaw(u_char ch);
+
+extern int AceRead(NUTFILE * fp, void *buffer, int size);
+extern int AceWrite(NUTFILE * fp, CONST void *buffer, int len);
+extern int AceWrite_P(NUTFILE * fp, PGM_P buffer, int len);
+extern NUTFILE *AceOpen(NUTDEVICE * dev, CONST char *name, int mode, int acc);
+extern long AceSize(NUTFILE * fp);
+extern int AceClose(NUTFILE * fp);
+
+__END_DECLS
+#endif

include/dev/adc.h

@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2004 by Ole Reinhardt <ole.reinhardt@kernelconcepts.de>,
+ *                       Kernelconcepts http://www.kernelconcepts.de
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ *
+ */
+ 
+/*!
+ * \file include/dev/adc.h
+ * \brief Header for AVR Adc driver
+ */
+
+/*!
+ * \addtogroup xgAvrAdc
+ */
+ 
+/*@{*/ 
+
+#ifndef _ADC_H_
+#define _ADC_H_
+
+// ENUM declaring possible ADC reference voltages
+//   - AVCC = 5V
+//   - AREF = External reference
+//   - INTERNAL_256 = 2.56V
+
+enum adc_ref_type
+{
+    AVCC	= 0,
+    AREF,
+    INTERNAL_256
+};
+
+typedef enum adc_ref_type adc_ref_t;
+
+// ENUM declaring possible ADC modes
+// FREE_RUNNING:
+//    Free-running mode. Samples continuously taken
+//    every 13 cycles of ADC clock after
+//    ADC_start_conversion() is called.
+// SINGLE_CONVERSION:
+//    Single-conversion mode. One sample taken every time
+//    ADC_start_conversion() is called.
+
+enum adc_mode_type
+{
+    ADC_OFF,
+    FREE_RUNNING,
+    SINGLE_CONVERSION
+};
+
+typedef enum adc_mode_type adc_mode_t;
+
+// ENUM declaring possible ADC channels
+
+enum adc_channel_type
+{
+    ADC0=0,
+    ADC1=1,
+    ADC2=2,
+    ADC3=3,
+    ADC4=4,
+    ADC5=5,
+    ADC6=6,
+    ADC7=7
+};
+
+typedef enum adc_channel_type adc_channel_t;
+
+#define ADC_PRESCALE_DIV2               0x00    ///< 0x01,0x00 -> CPU clk/2
+#define ADC_PRESCALE_DIV4               0x02    ///< 0x02 -> CPU clk/4
+#define ADC_PRESCALE_DIV8               0x03    ///< 0x03 -> CPU clk/8
+#define ADC_PRESCALE_DIV16              0x04    ///< 0x04 -> CPU clk/16
+#define ADC_PRESCALE_DIV32              0x05    ///< 0x05 -> CPU clk/32
+#define ADC_PRESCALE_DIV64              0x06    ///< 0x06 -> CPU clk/64
+#define ADC_PRESCALE_DIV128             0x07    ///< 0x07 -> CPU clk/128
+
+
+// ADC_Init                       
+//                                                    
+// This function initializes the ADC based on the
+//  #defines in config.h                       
+//                                                    
+// post: ADC initialized and primed for call to
+//       start_conversion
+
+void ADCInit(void);
+
+
+// ADC_SetRef                      
+//                                                    
+// Allows setting of reference voltage for ADC.
+//
+// NOTE: This function stops ADC conversion. One must
+//       call ADC_start_conversion to restart the ADC.
+//                                                    
+// pre: "reference" is a valid ADC reference from the
+//       choices given above
+// post: ADC conversion stopped and reference voltage
+//       set to desired choice
+
+void ADCSetRef(adc_ref_t reference);
+
+
+// ADC_SetMode                      
+//                                                    
+// Allows setting of ADC conversion mode: either
+// single-conversion or free-running.
+//
+// NOTE: This function stops ADC conversion. One must
+//       call ADC_start_conversion to restart the ADC.
+//                                                    
+// pre: "mode" is a valid ADC reference from the
+//       choices given above
+// post: ADC conversion stopped and the ADC mode is
+//       set to desired choice
+
+void ADCSetMode(adc_mode_t mode);
+
+
+// ADC_SetPrescale
+//                                                    
+// Allows setting of ADC clock prescalar (ADC rate).
+// The  ADC rate is given by the system clock rate
+// divided by the prescalar value. Possible prescalar
+// values range from 2-128 in powers of 2 (2,4,8,etc.)
+//
+// NOTE: This function stops ADC conversion. One must
+//       call ADC_start_conversion to restart the ADC.
+//                                                    
+// pre: "prescalar" is a valid ADC reference from the
+//       choices given above
+// post: ADC conversion stopped and ADC prescalar
+//       set to desired choice
+
+u_char ADCSetPrescale(u_char prescalar);
+
+
+// ADC_SetChannel
+//                                                    
+// Sets the channel that the ADC reads. The ADC
+// may only read from one channel at a time.
+//                                                    
+// pre: "adc_channel" is a valid ADC reference from the
+//       choices given above
+// post: ADC conversion stopped and ADC channel
+//       set to desired choice
+
+void ADCSetChannel(adc_channel_t adc_channel);
+
+
+// ADC_BufferFlush
+//                                                    
+// Flushes the local buffer used to store ADC values
+// between conversion and the user's call to ADC_read
+//
+// NOTE: It is recommended that one calls buffer flush
+//       if any changes are made to the ADC's state.
+//                                                    
+// pre: none
+// post: Local ADC buffer has been flushed
+
+void ADCBufferFlush(void);
+
+
+// ADC_StartConversion
+//                                                    
+// Begins ADC conversion. If in single-conversion mode,
+// this function will only convert one value. If in
+// free-running mode, this function will begin
+// continuous conversion at the rate set by the
+// prescalar (see ADC_set_prescalar).
+//
+// NOTE: Converted values from the ADC are stored
+//       in a local buffer. The user must call
+//       ADC_read to obtain these values.
+//
+// pre:  none
+// post: The ADC has started conversion. Completion of
+//       any conversions is not guaranteed.
+
+void ADCStartConversion(void);
+
+
+// ADC_StartLowNoiseConversion
+//                                                    
+// Set Conversion Mode to SINGLE_CONVERSION, Enters 
+// adc sleep mode and wait until conversion interrupt occurs.
+// CPU will go to sleep mode!!!
+// BE AWARE OF WHAT IS WRITTEN IN THE AVR DATASHEET
+//
+// NOTE: Converted values from the ADC are stored
+//       in a local buffer. The user must call
+//       ADC_read to obtain these values.
+//
+//       Only implemented for avr_gcc. Any other architecture 
+//       and compiler will use normal conversion
+// pre:  none
+// post: The ADC has started conversion. Completion of
+//       any conversions is not guaranteed.
+
+
+void ADCStartLowNoiseConversion(void);
+
+// ADC_StopConversion
+//                                                    
+// Stops ADC conversion if ADC is in free-running
+// mode. Has no effect if ADC is in single-conversion
+// mode.
+//
+// pre:  none
+// post: ADC conversion has been stopped.
+
+void ADCStopConversion(void);
+
+
+// ADC_read
+//                                                    
+// Reads ADC values from local buffer. Reads one ADC
+// conversion value at a time.
+//
+// return: 0 = OK
+//         1 = No ADC value to read. "value" is invalid
+//
+// pre:  "value" points to a valid variable.
+// post: If no errors, one ADC conversion value has
+//       been read and placed in the variable pointed
+//       to by "value"
+
+u_char ADCRead(u_short *value);
+
+// ADC_GetMode
+// returns current conversion mode
+
+inline adc_mode_t ADCGetMode(void);
+
+#endif
+/*@}*/

include/dev/ahdlc.h

@@ -0,0 +1,181 @@
+#ifndef _DEV_AHDLC_H_
+#define _DEV_AHDLC_H_
+
+/*
+ * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: ahdlc.h,v $
+ * Revision 1.1.1.1  2003/05/09 14:41:05  haraldkipp
+ * Initial using 3.2.1
+ *
+ * Revision 1.2  2003/05/06 18:40:28  harald
+ * Unused items removed
+ *
+ * Revision 1.1  2003/03/31 14:53:23  harald
+ * Prepare release 3.1
+ *
+ */
+
+#include <dev/netbuf.h>
+#include <net/if_var.h>
+
+
+/*!
+ * \file dev/ahdlc.h
+ * \brief Asynchronous HDLC device definitions.
+ */
+
+/*
+ * Significant octet values.
+ */
+#define AHDLC_ALLSTATIONS 0xff    /*!< \brief All-Stations broadcast address */
+#define AHDLC_UI          0x03    /*!< \brief Unnumbered Information */
+#define AHDLC_FLAG        0x7e    /*!< \brief Flag Sequence */
+#define AHDLC_ESCAPE      0x7d    /*!< \brief Asynchronous Control Escape */
+#define AHDLC_TRANS       0x20    /*!< \brief Asynchronous transparency modifier */
+
+/*
+ * Values for FCS calculations.
+ */
+#define AHDLC_INITFCS     0xffff  /*!< \brief Initial FCS value */
+#define AHDLC_GOODFCS     0xf0b8  /*!< \brief Good final FCS value */
+
+/*!
+ * \struct _AHDLCDCB ahdlc.h dev/ahdlc.h
+ * \brief Asynchronous HDLC device information structure.
+ *
+ * The start of this structure is equal to the UARTDCB structure.
+ */
+struct _AHDLCDCB {
+    
+    /*! \brief Mode flags.
+     */
+    u_long dcb_modeflags;
+
+    /*! \brief Status flags.
+     */
+    u_long dcb_statusflags;
+
+    /*! \brief Read timeout.
+     */
+    u_long dcb_rtimeout;
+
+    /*! \brief Write timeout.
+     */
+    u_long dcb_wtimeout;
+
+    /*! \brief Queue of threads waiting for output buffer empty.
+     *
+     * Threads are added to this queue when the output buffer 
+     * is full or when flushing the output buffer.
+     */
+    HANDLE dcb_tx_rdy;
+
+    /*! \brief Queue of threads waiting for a character in the input buffer.
+     *
+     * Threads are added to this queue when the output buffer is
+     * empty.
+     */
+    HANDLE dcb_rx_rdy;
+
+    /*! \brief Hardware base address.
+     * 
+     * This is a copy of the base address in the NUTDEVICE structure
+     * and required by the interrupt routine.
+     */
+    u_char dcb_base;
+
+    /*! \brief Input buffer. 
+     *
+     * This buffer is filled by the the receiver interrupt, so the
+     * contents of the buffer is volatile.
+     */
+    volatile u_char *dcb_rx_buf;
+    
+    /*! \brief Input buffer index for next incoming byte.
+     *
+     * This volatile index is incremented by the receiver interrupt.
+     */
+    volatile u_char dcb_rx_idx;
+
+    /*! \brief Input buffer index for next byte to read.
+     */
+    u_char dcb_rd_idx;
+
+    /*! \brief Output buffer. 
+     */
+    u_char *dcb_tx_buf;
+
+    /*! \brief Output buffer index for next outgoing byte. 
+     *
+     * This volatile index is incremented by the transmit interrupt.
+     */
+    volatile u_char dcb_tx_idx;
+
+    /*! \brief Output buffer index for next byte to write. 
+     */
+    u_char dcb_wr_idx;
+
+    /*! \brief HDLC mode change event queue.
+     *
+     * The frame receiver thread is waiting on this queue until
+     * the device is switched to HDLC mode.
+     */
+    HANDLE dcb_mf_evt;
+
+    /*! \brief 32-bit receive ACCM.
+     */
+    u_long dcb_rx_accm;         
+
+    /*! \brief 256-bit transmit ACCM.
+     */
+    u_long dcb_tx_accm;
+
+    /*! \brief Maximum receive MRU.
+     */
+    u_short dcb_rx_mru;
+
+    /*! \brief Maximum transmit MRU.
+     */
+    u_short dcb_tx_mru;
+
+};
+
+/*!
+ * \brief Asynchronous HDLC device information type.
+ */
+typedef struct _AHDLCDCB AHDLCDCB;
+
+
+#endif
+

include/dev/ahdlcavr.h

@@ -0,0 +1,80 @@
+#ifndef _DEV_AHDLCAVR_H_
+#define _DEV_AHDLCAVR_H_
+
+/*
+ * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: ahdlcavr.h,v $
+ * Revision 1.2  2004/03/16 16:48:28  haraldkipp
+ * Added Jan Dubiec's H8/300 port.
+ *
+ * Revision 1.1  2004/03/09 11:49:52  haraldkipp
+ * Added
+ *
+ */
+
+#include <dev/netbuf.h>
+#include <net/if_var.h>
+#include <dev/ahdlc.h>
+
+/*!
+ * \file dev/ahdlcavr.h
+ * \brief On-chip UART HDLC device definitions.
+ */
+
+
+/*
+ * Available drivers.
+ */
+extern NUTDEVICE devAhdlc0;
+extern NUTDEVICE devAhdlc1;
+
+extern int AhdlcAvrInit(NUTDEVICE *dev);
+extern int AhdlcAvrIOCtl(NUTDEVICE *dev, int req, void *conf);
+extern int AhdlcAvrInput(NUTDEVICE *dev);
+extern int AhdlcAvrOutput(NUTDEVICE *dev);
+extern int AhdlcAvrFlush(NUTDEVICE *dev);
+
+extern int AhdlcAvrGetRaw(u_char *cp);
+extern int AhdlcAvrPutRaw(u_char ch);
+
+extern int AhdlcAvrRead(NUTFILE *fp, void *buffer, int size);
+extern int AhdlcAvrWrite(NUTFILE *fp, CONST void *buffer, int len);
+#ifdef __HARVARD_ARCH__
+extern int AhdlcAvrWrite_P(NUTFILE *fp, PGM_P buffer, int len);
+#endif
+extern NUTFILE *AhdlcAvrOpen(NUTDEVICE *dev, CONST char *name, int mode, int acc);
+extern int AhdlcAvrClose(NUTFILE *fp);
+
+#endif
+

include/dev/at45db.h

@@ -0,0 +1,70 @@
+#ifndef _DEV_AT45DB_H_
+#define _DEV_AT45DB_H_
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*!
+ * \file dev/at45db.h
+ * \brief Dataflash helper routines.
+ *
+ * \verbatim
+ *
+ * $Log: at45db.h,v $
+ * Revision 1.2  2006/10/08 16:48:09  haraldkipp
+ * Documentation fixed
+ *
+ * Revision 1.1  2006/09/29 12:41:55  haraldkipp
+ * Added support for AT45 serial DataFlash memory chips. Currently limited
+ * to AT91 builds.
+ *
+ *
+ * \endverbatim
+ */
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+/* Prototypes */
+extern int At45dbSendCmd(int dd, u_char op, u_long parm, int len, CONST void *tdata, void *rdata, int datalen);
+extern u_char At45dbGetStatus(int dd);
+extern int At45dbWaitReady(int dd, u_long tmo, int poll);
+extern int At45dbInit(u_int spibas, u_int spipcs);
+extern int At45dbPageErase(int dd, u_int off);
+extern int At45dbChipErase(void);
+extern int At45dbPageRead(int dd, u_long pgn, void *data, u_int len);
+extern int At45dbPageWrite(int dd, u_int off, CONST void *data, u_int len);
+extern int At45dbParamRead(u_int pos, void *data, u_int len);
+extern int At45dbParamWrite(u_int pos, CONST void *data, u_int len);
+
+__END_DECLS
+/* End of prototypes */
+#endif

include/dev/at49bv.h

@@ -0,0 +1,59 @@
+#ifndef _DEV_AT49BV_H_
+#define	_DEV_AT49BV_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: at49bv.h,v $
+ * Revision 1.1  2006/04/07 13:51:36  haraldkipp
+ * AT49BV flash memory support added. A single sector may be used to
+ * store system configurations in case there is no EEPROM available.
+ *
+ */
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+/* Prototypes */
+
+extern unsigned long At49bvInit(void);
+extern int At49bvChipErase(void);
+extern int At49bvSectorErase(u_int off);
+extern int At49bvSectorRead(u_int off, void *data, u_int len);
+extern int At49bvSectorWrite(u_int off, CONST void *data, u_int len);
+extern int At49bvParamRead(u_int pos, void *data, u_int len);
+extern int At49bvParamWrite(u_int pos, CONST void *data, u_int len);
+
+__END_DECLS
+/* End of prototypes */
+#endif

include/dev/at91_efc.h

@@ -0,0 +1,26 @@
+#ifndef _DEV_AT91_EFC_H_
+#define _DEV_AT91_EFC_H_
+
+#include <sys/types.h>
+
+/*!
+ * \brief Load data from MCU on-chip flash.
+ *
+ * \return 0 on success, -1 otherwise.
+ */
+extern int OnChipFlashLoad(u_long addr, void *buff, size_t siz);
+
+/*!
+ * \brief Save data to MCU on-chip flash.
+ *
+ * \return 0 on success, -1 otherwise.
+ */
+extern int OnChipFlashSave(u_long addr, CONST void *buff, size_t len);
+
+extern int FlashAreaIsLock(u_long addr);
+
+extern int LockFlashArea(u_long addr);
+
+extern int UnlockFlashArea(u_long addr);
+
+#endif

include/dev/at91_emac.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: at91_emac.h,v $
+ * Revision 1.1  2006/08/31 18:58:47  haraldkipp
+ * More general AT91 MAC driver replaces the SAM7X specific version.
+ * This had been tested on the SAM9260, but loses Ethernet packets
+ * for a yet unknown reason.
+ *
+ * Revision 1.1  2006/07/05 07:38:44  haraldkipp
+ * New Ethernet driver for the AT91SAM7X EMAC and the Davicom DM9161A.
+ * This driver is not yet finished. Ethernet link auto-negotiation works
+ * and receive interrupts are generated when sending packets to the
+ * board. But transmitting packets fails, nothing is sent out.
+ *
+ */
+
+#ifndef _DEV_AT91SAM7X_EMAC_H_
+#define _DEV_AT91SAM7X_EMAC_H_
+
+#include <sys/device.h>
+#include <net/if_var.h>
+
+/*
+ * Available drivers.
+ */
+extern NUTDEVICE devAt91Emac;
+
+#ifndef DEV_ETHER
+#define DEV_ETHER   devAt91Emac
+#endif
+
+#ifndef devEth0
+#define devEth0   devAt91Emac
+#endif
+
+#endif

include/dev/at91_mci.h

@@ -0,0 +1,51 @@
+#ifndef _DEV_AT91_MCI_H_
+#define _DEV_AT91_MCI_H_
+
+/*
+ * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+/*
+ * $Log: at91_mci.h,v $
+ * Revision 1.1  2006/09/05 12:34:21  haraldkipp
+ * Support for hardware MultiMedia Card interface added.
+ * SD Cards are currently not supported.
+ *
+ */
+
+#include <sys/device.h>
+
+/*
+ * Available drivers.
+ */
+extern NUTDEVICE devAt91Mci0;
+
+#endif                          /* _DEV_AT91_MCI_H_ */