ih_tc0.c 4.5 KB

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  1. /*!
  2. * Copyright (C) 2001-2010 by egnite Software GmbH
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the copyright holders nor the names of
  16. * contributors may be used to endorse or promote products derived
  17. * from this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  26. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  27. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  29. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30. * SUCH DAMAGE.
  31. *
  32. * For additional information see http://www.ethernut.de/
  33. */
  34. /*
  35. * $Log: ih_tc0.c,v $
  36. *
  37. */
  38. #include <arch/avr32.h>
  39. #include <dev/irqreg.h>
  40. #include <avr32/io.h>
  41. #include <arch/avr32/ihndlr.h>
  42. #ifndef NUT_IRQPRI_TC0
  43. #define NUT_IRQPRI_TC0 0
  44. #endif
  45. #define CHANNEL 0
  46. #ifndef NUT_IRQCHANNEL_TC0
  47. #define NUT_IRQCHANNEL_TC0 AVR32_TC0_IRQ0
  48. #endif
  49. // Some devices with only 1 TC like A0512 will define it as TC instead of TC0
  50. #if !defined(AVR32_TC0) && defined( AVR32_TC )
  51. # define AVR32_TC0 AVR32_TC
  52. # define AVR32_TC0_IRQ0 AVR32_TC_IRQ0
  53. #endif
  54. static int TimerCounter0IrqCtl(int cmd, void *param);
  55. IRQ_HANDLER sig_TC0 = {
  56. #ifdef NUT_PERFMON
  57. 0, /* Interrupt counter, ir_count. */
  58. #endif
  59. NULL, /* Passed argument, ir_arg. */
  60. NULL, /* Handler subroutine, ir_handler. */
  61. TimerCounter0IrqCtl /* Interrupt control, ir_ctl. */
  62. };
  63. /*!
  64. * \brief UART 0 interrupt entry.
  65. */
  66. SIGNAL(TC0IrqEntry)
  67. {
  68. IRQ_ENTRY();
  69. #ifdef NUT_PERFMON
  70. sig_TC0.ir_count++;
  71. #endif
  72. if (sig_TC0.ir_handler) {
  73. (sig_TC0.ir_handler) (sig_TC0.ir_arg);
  74. }
  75. IRQ_EXIT();
  76. }
  77. /*!
  78. * \brief Timer/Counter 0 interrupt control.
  79. *
  80. * \param cmd Control command.
  81. * - NUT_IRQCTL_INIT Initialize and disable interrupt.
  82. * - NUT_IRQCTL_STATUS Query interrupt status.
  83. * - NUT_IRQCTL_ENABLE Enable interrupt.
  84. * - NUT_IRQCTL_DISABLE Disable interrupt.
  85. * - NUT_IRQCTL_GETMODE Query interrupt mode.
  86. * - NUT_IRQCTL_SETMODE Set interrupt mode (NUT_IRQMODE_LEVEL or NUT_IRQMODE_EDGE).
  87. * - NUT_IRQCTL_GETPRIO Query interrupt priority.
  88. * - NUT_IRQCTL_SETPRIO Set interrupt priority.
  89. * - NUT_IRQCTL_GETCOUNT Query and clear interrupt counter.
  90. * \param param Pointer to optional parameter.
  91. *
  92. * \return 0 on success, -1 otherwise.
  93. */
  94. static int TimerCounter0IrqCtl(int cmd, void *param)
  95. {
  96. int rc = 0;
  97. unsigned int *ival = (unsigned int *) param;
  98. ureg_t imr = AVR32_TC0.channel[CHANNEL].imr;
  99. static ureg_t enabledIMR = 0;
  100. int_fast8_t enabled = imr;
  101. /* Disable interrupt. */
  102. if (enabled) {
  103. AVR32_TC0.channel[CHANNEL].idr = 0xFFFFFFFF;
  104. AVR32_TC0.channel[CHANNEL].sr;
  105. enabledIMR = imr;
  106. }
  107. switch (cmd) {
  108. case NUT_IRQCTL_INIT:
  109. register_interrupt(TC0IrqEntry, NUT_IRQCHANNEL_TC0, NUT_IRQPRI_TC0);
  110. break;
  111. case NUT_IRQCTL_STATUS:
  112. if (enabled) {
  113. *ival |= 1;
  114. } else {
  115. *ival &= ~1;
  116. }
  117. break;
  118. case NUT_IRQCTL_ENABLE:
  119. enabled = 1;
  120. break;
  121. case NUT_IRQCTL_DISABLE:
  122. enabled = 0;
  123. break;
  124. #ifdef NUT_PERFMON
  125. case NUT_IRQCTL_GETCOUNT:
  126. *ival = (unsigned int) sig_TC0.ir_count;
  127. sig_TC0.ir_count = 0;
  128. break;
  129. #endif
  130. default:
  131. rc = -1;
  132. break;
  133. }
  134. /* Enable interrupt. */
  135. if (enabled) {
  136. AVR32_TC0.channel[CHANNEL].ier = enabledIMR;
  137. AVR32_TC0.channel[CHANNEL].sr;
  138. }
  139. return rc;
  140. }